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Chapter 4: Configuring the Emulator
Configuring the Emulator Pod
To enable/disable emulation memory
synchronization
• Answer "yes" to the "Interlock emulator /DTACK with user /DTACK?" question to
enable synchronization; answer "no" to disable synchronization.
/DTACK interlock applies only to situations where the 68302 does not provide an
internal /DTACK. The 68302 processor can generate internal /DTACK signals for
chip selects or internal processor cycles. (The source of the emulator /DTACK for
chip selects is specified by answering the "/DTACK source for chip select"
configuration questions.) If the /DTACK is internally generated, it will be driven
to the target system, and the emulator will not drive /DTACK to the processor.
Also, /DTACK interlock applies only when you are operating the emulator
in-circuit (that is, plugged into a target system). If you are operating the emulator
out-of-circuit, all emulation and background monitor accesses are completed by the
emulator-generated /DTACK signal, regardless of the answer to this configuration
question.
When /DTACK interlock is enabled:
When /DTACK interlock is disabled:
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Accesses to emulation memory will not be terminated until the target system
provides a /DTACK.
If background cycles are being driven to the target system (see the following
"Drive background cycles to the target system?" question), the target system
must provide a /DTACK signal to terminate background memory cycles.
If a /BERR signal occurs during an emulation memory cycle when bus error
response is enabled (see the following "Enable Bus Error on emulation
memory accesses?" question), the cycle will be terminated, and the emulation
processor will begin executing the bus error handler.
Emulation memory and background monitor accesses are terminated with a
/DTACK signal generated by the emulator.
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