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Chapter 5: Plugging into a Target System
Configuring the Emulator for In-Circuit Operation
Step 5. Decide whether to use the foreground
monitor
The default configuration for the 68302 emulator uses the background monitor.
The background monitor is easier to use and usually requires no special setup.
The foreground monitor offers you much more flexibility but also requires extra
setup and sometimes requires more in-depth knowledge of your target system. You
should use the foreground monitor if any of the following are true:
•
•
•
•
•
Note that some users choose the foreground monitor so that they can customize it to
refresh the on-chip watchdog timer of the 68302; however, this is not necessary.
The 68302 SCR register contains a bit which, when set, will suspend the watchdog
timer whenever the FRZ pin is asserted. This bit is called "FRZW". You can
simply modify your code to set that bit on startup, and the watchdog timer will
automatically be suspended when you are in the background monitor.
If you do choose to use the foreground monitor, you cannot take advantage of the
FRZW feature since the FRZ pin is only asserted in the background monitor. Note
that the FRZ1 and FRZ2 bits of the SCR can likewise be used to suspend timer1
and timer2 during background operation.
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Your target system has DRAM, and you use the built-in DRAM refresh of the
68302 to refresh it
You need to service some type of interrupt even when you are running in the
monitor. An example of this is might be a timer interrupt that MUST be
serviced on a regular interval
You need to have SCC functions occurring while you are running in the
monitor
You need to customize the monitor to provide some special function, such as
servicing an off-chip watchdog timer
You have frequent external interrupts occurring and this prevents you from
being able to single-step correctly. This problem can occur when external
interrupts are left pending during background execution. The problem will
appear as a PC that is "stuck" at the same address after each step command.
(One solution to this problem is to modify the processor status register to raise
the interrupt mask before stepping, and then restoring it after you are finished
stepping.)
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