Read-Only Memory (Rom); Random Access Memory (Ram); Direct Memory Access (Dma); Sdlc And Bisync Data Communication - HP 3000 Series Installation And Service Manual

Principles of Operation
requires the use of logic buffers that convert CMOS/SOS levels to
the more conventional TTL signal levels. The INP Microprocessor
instruction set has been optimized for efficient operations per-
formed directly on the I/O registers.
The INP Microprocessor is designed to facilitate functions such
as logical decision making, indexed branches, and external event
synchronization. These capabilities allow the INP Microprocessor
to efficiently perform the functions required of an intelligent
network processor.
4-3. Read-Only Memory (ROM)
The INP has a 2K word, high-speed CMOS/SOS ROM. The ROM contains
power- on and reset programs, functional diagnostics, loader/
dumper routines, and RAM fault location code.
4-4. Random Access Memory (RAM)
The INP has 16K words of dynamic RAM that store the protocol
driver in use (such as BISYNC point-to-point), the INP's control
program, the HP 3000 interface driver, and data buffers for the
commun ica tion channel.
Several circuits are required to support and insure the reliable
operation of the RAM. A refresh circuit is provided to refresh
(or renewl) the contents of the dynamic RAM at regular intervals.
An LSI chip also aids in performing this function. A parity cir-
cuit calculates a parity bit on each byte written to RAM and
verifies the bit on each read from RAM. Memory-protect circuitry
and separate power supply lines are provided for the RAM, RAM
refresh circuitry, and other associated support circuitry to
assure that no data will be lost in the event of a power failure
or ''br ownout" •
4-5. Direct Memory Access (DMA)
The INP uses an LSI DMA-controller chip to provide three
highspeed channels between data buffers in RAM and the HP-IB
Interface, as well as between RAM and datacomm LSI devices. The
function of the DMA logic is to move bytes between external
devices and RAM in such a way that they will be transparent to
the INP Microprocessor software. This ability to transfer data
concurrently with instruction execution enables the INP to
achieve high throughput rates.
4-6. SDLC and BISYNC Data Communication
The INP uses LSI datacomm devices that are programmed by the INP
Microprocessor to operate with BISYNC and SDLC protocols. When
transmitting, these devices receive data and control bytes in
4-3