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Analyzing the PowerPC 604
Using the Inverse Assembler
Show/Suppress
The enhanced inverse assembler (I604E) supports selective suppression of
certain states in the state listing display. The show/suppress settings do not
affect the data that is stored by the logic analyzer; they only affect whether
that data is displayed or not. The same data can be examined with different
settings, for different analysis requirements. The figure below shows the
states that have the Show/Suppress option.
604 Inverse Assembly Options
Code Synchronization
(
)
1-lait/idle states
Show
from (
Start
0
I
8
Instructions
(
Show
l
(
J
Probable overfetch
(
Show
)
A 1 i gn
Possible overfetch
(
Show
J
(
)
Dialect
Raw
(
)
Operand reads
Show
(10
%
10)
Numerics
10'
Operand writes
(
Show
)
hex
dee
bin
Address-only states
(
Show
J
(
)
Separator
Space
(
Done
J
Suppressing wait/idle states is useful for obtaining a state-per-cycle display of
acquired data. Suppressing overfetched instructions may assist in following
program execution trace more clearly. Suppressing instructions may be
useful
if
your primary interest is data operand reads and writes.
"Probable overfetch" means states marked with a"*" or
11 - 11 •
"Possible
overfetch" means states marked with a
"?".
When instructions are suppressed, the overfetch show/suppress controls
have no effect.
This function allows faster analysis in two ways. First, unneeded information
can be filtered out of the display. Second, particular operations can be
isolated by suppressing all other operations. For example, memory writes
can be shown, with all other operations suppressed, allowing quick analysis of
memory writes.
E2465A PowerPC 604 PGA Preprocessor
2-19
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