Table 3-1 Srom Power-Up Status Messages - Compaq ES40CSLP Installation, User & Service Manual

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The primary CPU (usually CPU0) initializes and tests the B-cache and memory, then
loads the flash SROM code to the next CPU. That CPU then initializes the EV6 (21264
chip) and marks itself as the secondary CPU. Once the primary CPU sees the secondary,
it loads the flash SROM code to the next CPU until all remaining CPUs are loaded.
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The Flash SROM performs various B-cache tests. For example, the ECC data test verifies
the detection logic for single- and double-bit errors.
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The primary CPU initiates all memory tests. The memory is tested for address and data
errors for the first 32 MB of memory. It also initializes all of the "sized" memory in the
system.
If a memory failure occurs, an error is reported. An untested memory array is assigned to
address 0 and the failed memory array is de-assigned. The memory tests are re-run on the
first 32 MB of memory. If all memory fails, the "No Memory Available" message is
reported and the system halts.
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If all memory passes, the primary CPU loads the SRM console and transfers control to
it.

Table 3-1 SROM Power-Up Status Messages

Status
Code Full SROM Message
DF SROM program starting
DE Init and test PCI bus
DD Bcache data tests in progress
DC Bcache address test in progress
DB CPU parity and ECC error detection in progress
DA Bcache ECC data tests in progress
D8 Bcache TAG lines tests in progress
D7 Reloading SROM
D5 Memory sizing in progress
D4 Memory configuration in progress
D3 Memory data test in progress
D2 Memory address test in progress
D1 Memory pattern test in progress
D0 Memory thrashing test in progress
CF Memory initialization
CD Loading console
CB Code execution complete (transfer control)
C5 Loading program from floppy
93 Starting secondary on CPU #3
92 Starting secondary on CPU #2
91 Starting secondary on CPU #1
90 Starting secondary on CPU #0
Compaq ES40CSLP Rackmount System Installation/User/Service Guide 3–3
Operation
Corresponding
OCP Message
Power on
PCI Test
BC Data
BC Addr
Par/ECC
BC ECC
BC Tag
Reload
Size Mem
Cfg Mem
Mem Data
Mem Addr
Mem Patt
Mem thra
Mem Init
Load ROM
Jump to Console.
Load Flp
RelCPU 3
RelCPU 2
RelCPU 1
RelCPU 0