Srom Power-Up Display; Example 6-1 Sample Srom Power-Up Display - Compaq ES40CSLP Installation, User & Service Manual

6.5.4 SROM Power-Up Display

Power-up information is displayed on the system's console terminal and the control panel. If the
SRM console environment variable is set to serial, the entire power-up display, consisting of
the SROM and SRM power-up messages, is printed on the VT terminal screen. If console is set
to graphics, no SROM messages are displayed, and the SRM messages are delayed until VGA
initialization has been completed. This process can take a little while
Example 6-1 shows the SROM power-up messages and corresponding operator control panel
messages. See Table 6-7 for the full list of SROM and OCP start-up messages.

Example 6-1 Sample SROM Power-Up Display

SROM Power-Up Display
SROM V1.00 CPU #00 @
SROM program starting
Reloading SROM
SROM V1.00-F CPU # 00 @
SROM program starting
Starting secondary on CPU #1
Starting secondary on CPU #2
Starting secondary on CPU #3
Bcache data tests in progress
Bcache address test in progress
CPU parity and ECC detection in progress
Bcache ECC data tests in progress
Bcache TAG lines tests in progress
Memory sizing in progress
Memory configuration in progress
Memory data test in progress
Memory address test in progress
Memory pattern test in progress
Memory thrashing test in progress
Memory initialization
Loading console
Code execution complete (transfer control)
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When the system is powered up, the serial SROM code is loaded into the I-cache on the
first available CPU, which becomes the primary CPU. The order of precedence is CPU0,
CPU1, and so on. The primary CPU attempts to access the PCI bus. If it cannot, either a
hang or a failure occurs and this is the only message displayed.
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The primary CPU interrogates the I
modules through the shared dual-port RAM (DPR). Using the acquired data, the primary
CPU determines the CPU and system configuration to jump to.
The primary CPU next checks the SROM checksum to determine the validity of the Flash
SROM sectors.
If Flash SROM is invalid, the primary CPU reports the error and continues the execution of
the serial SROM code. The Flash SROM must be reprogrammed in this case.
If Flash SROM is good, the primary CPU programs the appropriate registers with the values
from the Flash data and selects itself as a target CPU to be loaded.
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The CPU loaded into Flash ROM (usually CPU0) initializes and tests the B-cache and
memory, then loads the Flash SROM code to the next CPU. The loaded CPU initializes the
EV6 (21264 chip) and marks itself as the secondary CPU. Once the primary CPU sees the
secondary, it loads the Flash SROM code to the next CPU until all CPUs are loaded.
0500 MHz
0500 MHz
2
C EEROM on the system motherboard and CPU
Compaq ES40CSLP Rackmount System Installation/User/Service Guide 6–11
Troubleshooting and Diagnostics
OCP Message
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PCI Test
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Power on
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RelCPU
›
BC Data
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Size Mem
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Load ROM
Jump to Console