User Manuals: Segger J-Trace Debug Probes

Manuals and User Guides for Segger J-Trace Debug Probes. We have 8 Segger J-Trace Debug Probes manuals available for free PDF download: User Manual

Segger J-Trace User Manual

Segger J-Trace User Manual (480 pages)

Brand: Segger | Category: Adapter | Size: 4 MB

Table of Contents

Table of Contents
17
Introduction
27
Requirements
28
Supported os
29
J-Link / J-Trace Models
30
Model Comparison
31
J-Link BASE
32
J-Link PLUS
34
J-Link ULTRA
37
J-Link PRO
39
J-Link Lite Cortexm
41
J-Trace ARM
42
J-Trace for Cortex-M
43
Flasher ARM
45
Common Features of the J-Link Product Family
47
Supported CPU Cores
48
Built-In Intelligence for Supported CPU-Cores
49
Firmware Intelligence Per Model
51
Supported Ides
53
Licensing
55
Built-In License
57
Legal Use of SEGGER J-Link Software
58
Original SEGGER Products
59
J-Link ULTRA
60
J-Trace for Cortex-M
61
Flasher ARM
62
- Flasher PPC
  63
- J-Link OEM Versions
  64
- Digi: JTAG Link
  65
- IAR: J-Trace
  66
- J-Link Obs
  67
- Illegal Clones
  68
3 J-Link Software and Documentation Package

69
- Software Overview
  70
- J-Link Commander (Command Line Tool)
  71
- Commands
  72
- Command Line Options
  88
- Using Command Files
  91
- J-Link GDB Server
  92
- Debugging with J-Link GDB Server
  93
- Supported Remote (Monitor) Commands
  98
- SEGGER-Specific GDB Protocol Extensions
  110
- Command Line Options
  115
- Program Termination
  126
- Semihosting
  127
- J-Link Remote Server
  128
- Tunneling Mode
  129
- J-Mem Memory Viewer
  132
- J-Flash
  133
- J-Link RTT Viewer
  134
- Connection Settings
  135
- Sending Input
  136
- Logging Data
  137
- Menus and Shortcuts
  139
- Using "Virtual" Terminals in RTT
  141
- J-Link SWO Viewer
  142
- Usage
  143
- Configure SWO Output after Device Reset
  145
- SWO Analyzer
  148
- Jtagload (Command Line Tool)
  149
- J-Link RDI (Remote Debug Interface)
  150
- Processor Specific Tools
  151
- J-Link STM32 Unlock (Command Line Tool)
  152
  - J-Link Software Developer Kit (SDK)
    155
  - Setup
    157
  - Installing the J-Link Software and Documentation Pack
    158
  - Setting up the USB Interface
    161
  - Uninstalling the J-Link USB Driver
    162
  - Setting up the IP Interface
    164
  - Faqs
    166
  - J-Link Configurator
    167
  - J-Link USB Identification
    169
  - Using the J-Link DLL
    171
  - Determining the Version of Jlink DLL
    172
  - Getting Started with J-Link and ARM DS-5
    173
5 Working with J-Link and J-Trace

175
- Connecting the Target System
  176
- Indicators
  177
- Input Indicator
  179
- JTAG Interface
  180
- Determining Values for Scan Chain Configuration
  183
- JTAG Speed
  184
- SWD Interface
  185
- Multi-Core Debugging
  187
- Using Multi-Core Debugging in Detail
  188
- Things You Should be Aware of
  189
- Connecting Multiple J-Links / J-Traces to Your PC
  191
- J-Link Control Panel
  193
- Reset Strategies
  199
- Strategies for Cortex-M Devices
  201
- Using DCC for Memory Access
  204
- The J-Link Settings File
  205
- J-Link Script Files
  206
- Script File API Functions
  208
- Global DLL Variables
  213
- Global DLL Constants
  217
- Script File Language
  219
- Script File Writing Example
  220
  - Command Strings
    223
- Using Command Strings
  241
  - Switching off CPU Clock During Debug
    243
  - Cache Handling
    244
  - Virtual COM Port (VCOM)
    245
6 Flash Download

247
- Introduction
  248
- Licensing
  249
- Supported Devices
  250
- Setup for Various Debuggers (Internal Flash)
  251
- Mentor Sourcery Codebench
  254
- J-Link Commander
  255
- J-Link RDI
  256
- Setup for Various Debuggers (CFI Flash)
  257
- J-Link GDB Server
  258
- Setup for Various Debuggers (SPIFI Flash)
  259
- QSPI Flash Support
  260
- Using the DLL Flash Loaders in Custom Applications
  261
- Debugging Applications that Change Flash Contents at Runtime
  262
7 Flash Breakpoints

263
- Introduction
  264
- Licensing
  265
- Supported Devices
  266
- Setup & Compatibility with Various Debuggers
  267
- Flash Breakpoints in QSPI Flash
  268
8 Monitor Mode Debugging

271
- Introduction
  272
- Enable Monitor Debugging
  273
- Keil MDK-ARM (Uvision)
  274
- Availability and Limitations of Monitor Mode
  275
- Monitor Code
  276
- Debugging Interrupts
  277
- Having Servicing Interrupts in Debug Mode
  278
- Forwarding of Monitor Interrupts
  279
- Target Application Performs Reset (Cortex-M)
  280
9 Low Power Debugging

281
- Introduction
  282
- Activating Low Power Mode Handling for J-Link
  283
- Restrictions
  284

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Segger J-Trace User Manual

Segger J-Trace User Manual (368 pages)

Brand: Segger | Category: Computer Accessories | Size: 3 MB

Table of Contents

About this Document
13
Table of Contents
15
1 Introduction

22
2 Licensing

30
3 J-Link Software and Documentation Package

34
- Software Overview
  35
- J-Link Commander (Command Line Tool)
  36
  - Commands
    36
  - Command Line Options
    52
  - Using Command Files
    55
- J-Link GDB Server
  56
- J-Link Remote Server
  89
  - List of Available Commands
    89
  - Tunneling Mode
    89
- J-Mem Memory Viewer
  93
- J-Flash
  94
- J-Link RTT Viewer
  95
  - RTT Viewer Startup
    95
  - Connection Settings
    96
  - The Terminal Tabs
    96
  - Sending Input
    97
  - Logging Terminal Output
    97
  - Logging Data
    97
  - Command Line Options
    98
  - Menus and Shortcuts
    100
  - Using "Virtual" Terminals in RTT
    101
  - Using Text Control Codes
    101
- J-Link SWO Viewer
  103
  - Usage
    104
  - List of Available Command Line Options
    104
  - Configure SWO Output after Device Reset
    106
  - Target Example Code for Terminal Output
    107
- SWO Analyzer
  109
- Jtagload (Command Line Tool)
  110
- J-Link RDI (Remote Debug Interface)
  111
  - Flash Download and Flash Breakpoints
    111
- Processor Specific Tools
  112
  - J-Link Str91X Commander (Command Line Tool)
    112
  - J-Link STM32 Unlock (Command Line Tool)
    115
- J-Link Software Developer Kit (SDK)
  118
4 Setup

119
5 Working with J-Link and J-Trace

132
- Supported Ides
  133
- Connecting the Target System
  134
  - Power-On Sequence
    134
  - Verifying Target Device Connection
    134
  - Problems
    134
- Indicators
  135
  - Main Indicator
    135
  - Input Indicator
    135
  - Output Indicator
    136
- JTAG Interface
  137
  - Multiple Devices in the Scan Chain
    137
  - Sample Configuration Dialog Boxes
    137
  - Determining Values for Scan Chain Configuration
    139
  - JTAG Speed
    140
- SWD Interface
  141
  - SWD Speed
    141
  - Swo
    141
- Multi-Core Debugging
  143
- Connecting Multiple J-Links / J-Traces to Your PC
  146
  - How Does It Work
    146
- J-Link Control Panel
  148
  - Tabs
    148
- Reset Strategies
  154
  - Strategies for ARM 7/9 Devices
    154
  - Strategies for Cortex-M Devices
    155
- Using DCC for Memory Access
  159
  - What Is Required
    159
  - Target DCC Handler
    159
  - Target DCC Abort Handler
    159
- The J-Link Settings File
  160
  - SEGGER Embedded Studio
    160
  - Keil MDK-ARM (Uvision)
    160
  - Iar Ewarm
    160
  - Mentor Sourcery Codebench for ARM
    160
- J-Link Script Files
  161
  - Actions that Can be Customized
    161
  - Script File API Functions
    163
  - Global DLL Variables
    172
  - Global DLL Constants
    176
  - Script File Language
    178
  - Script File Writing Example
    179
  - Executing J-Link Script Files
    179
- Command Strings
  180
  - List of Available Commands
    180
  - Using Command Strings
    199
- Switching off CPU Clock During Debug
  201
- Cache Handling
  202
  - Cache Coherency
    202
  - Cache Clean Area
    202
  - Cache Handling of ARM7 Cores
    202
  - Cache Handling of ARM9 Cores
    202
- Virtual COM Port (VCOM)
  203
  - Configuring Virtual COM Port
    203
6 Flash Download

205
- Introduction
  206
- Licensing
  207
- Supported Devices
  208
- Setup for Various Debuggers (Internal Flash)
  209
- Setup for Various Debuggers (CFI Flash)
  210
- Setup for Various Debuggers (SPIFI Flash)
  211
- QSPI Flash Support
  212
  - Setup the DLL for QSPI Flash Download
    212
- Using the DLL Flash Loaders in Custom Applications
  213
- Debugging Applications that Change Flash Contents at Runtime
  214
7 Flash Breakpoints

215
- Introduction
  216
- Licensing
  217
  - Free for Evaluation and Non-Commercial Use
    217
- Supported Devices
  218
- Setup & Compatibility with Various Debuggers
  219
  - Setup
    219
  - Compatibility with Various Debuggers
    219
- Flash Breakpoints in QSPI Flash
  220
  - Setup
    220
  - Faq
    221
8 Monitor Mode Debugging

222
- Introduction
  223
- Enable Monitor Debugging
  224
- Availability and Limitations of Monitor Mode
  225
  - Cortex-M3
    225
  - Cortex-M4
    225
- Monitor Code
  226
- Debugging Interrupts
  227
- Having Servicing Interrupts in Debug Mode
  228
- Forwarding of Monitor Interrupts
  229
- Target Application Performs Reset (Cortex-M)
  230
9 Low Power Debugging

231
- Introduction
  232
- Activating Low Power Mode Handling for J-Link
  233
- Restrictions
  234
10 Open Flashloader

235
- Introduction
  236
- General Procedure
  237
- Adding a New Device
  238
- Editing/Extending an Existing Device
  239
- XML Tags and Attributes
  240
  - Database
    240
  - Device
    240
  - Chipinfo
    240
  - Flashbankinfo
    242
- Example XML File
  244
- Add. Info / Considerations / Limitations
  245
  - CMSIS Flash Algorithms Compatibility
    245
  - Customized Flash Banks
    245
  - Supported Cores
    245
  - Information for Silicon Vendors
    245
  - Template Projects and How To's
    245

SEGGER J-Trace User Manual

SEGGER J-Trace User Manual (320 pages)

Brand: SEGGER | Category: Computer Accessories | Size: 3 MB

Table of Contents

About this Document
13
Table of Contents
15
1 Introduction

21
- Requirements
  22
- Supported os
  23
- J-Link / J-Trace Models
  24
- Model Comparison
  25
- J-Link
  26
- J-Link ULTRA
  29
- J-Link PRO
  30
- J-Link Lite ARM
  31
- J-Link Lite Cortex-M
  32
- J-Trace ARM
  33
- J-Trace for Cortex-M
  36
- Flasher ARM
  38
- J-Link Coldfire
  39
- Common Features of the J-Link Product Family
  40
- Supported CPU Cores
  41
- Built-In Intelligence for Supported CPU-Cores
  42
- Intelligence in the J-Link Firmware
  42
- Intelligence on the PC-Side (DLL)
  42
- Firmware Intelligence Per Model
  44
- Supported Ides
  46
2 Licensing

47
- Components Requiring a License48
  48
- License Types
  49
- Built-In License
  49
- Key-Based License
  49
- Legal Use of SEGGER J-Link Software
  50
- Use of the Software with 3Rd Party Tools
  50
- Original SEGGER Products
  51
- J-Link
  51
- J-Link PLUS
  51
- J-Link ULTRA
  52
- J-Link PRO
  52
- J-Trace
  53
- J-Trace for Cortex-M
  53
- Flasher ARM
  54
- Flasher ARM Is a Programming Tool for Microcontrollers with On-Chip or External
  54
- Licenses
  54
- Comes with Built-In Licenses for Flash Download and J-Flash.54
  54
- Flasher RX
  54
- Flasher PPC
  55
- J-Link OEM Versions
  56
- Analog Devices: Midaslink
  56
- Atmel: SAM-ICE
  56
- Digi: JTAG Link
  57
- IAR: J-Link / J-Link KS
  57
- IAR: J-Link Lite
  57
- IAR: J-Trace
  58
- NXP: J-Link Lite LPC Edition
  58
- SEGGER: J-Link Lite ARM
  58
- J-Link Obs
  59
- Illegal Clones
  60
3 Link Software and Documentation Package

61
- Software Overview
  62
- J-Link Commander (Command Line Tool)
  63
- Command Line Options
  63
- Using Command Files
  64
- J-Link GDB Server
  66
- J-Link GDB Server CL
  66
- Debugging with J-Link GDB Server
  67
- Supported Remote (Monitor) Commands
  71
- SEGGER-Specific GDB Protocol Extensions
  83
- Command Line Options
  86
- J-Link Remote Server
  96
- List of Available Commands
  96
- Tunneling Mode
  97
- J-Mem Memory Viewer
  100
- J-Flash
  101
- J-Link SWO Viewer
  102
- Usage
  103
- List of Available Command Line Options
  103
- Configure SWO Output after Device Reset
  105
- Target Example Code for Terminal Output
  105
- SWO Analyzer
  108
- Jtagload (Command Line Tool)
  109
- J-Link RDI (Remote Debug Interface)
  110
- Flash Download and Flash Breakpoints
  110
- Processor Specific Tools
  111
- J-Link Str91X Commander (Command Line Tool)
  111
- J-Link STM32 Unlock (Command Line Tool)
  112
- J-Link Software Developer Kit (SDK)
  114
4 Setup

115
5 Working with J-Link and J-Trace

133
- Connecting the Target System
  134
- Power-On Sequence
  134
- Verifying Target Device Connection
  134
- Problems
  134
- Indicators
  135
- Main Indicator
  135
- Input Indicator
  137
- Output Indicator
  137
- JTAG Interface
  138
- Multiple Devices in the Scan Chain
  138
- Sample Configuration Dialog Boxes
  138
- Determining Values for Scan Chain Configuration
  141
- JTAG Speed
  142
- SWD Interface
  143
- SWD Speed
  143
- Swo
  143
- Multi-Core Debugging
  145
- How Multi-Core Debugging Works
  145
- Using Multi-Core Debugging in Detail
  146
- Things You Should be Aware of
  147
- Connecting Multiple J-Links / J-Traces to Your PC
  149
- How Does It Work
  149
- J-Link Control Panel
  151
- Tabs
  151
- Reset Strategies
  157
- Strategies for ARM 7/9 Devices
  157
- Strategies for Cortex-M Devices
  159
- Using DCC for Memory Access
  162
- What Is Required
  162
- Target DCC Handler
  162
- Target DCC Abort Handler
  162
- J-Link Script Files
  163
- Actions that Can be Customized
  163
- Script File API Functions
  163
- Global DLL Variables
  167
- Global DLL Constants
  170
- Script File Language
  171
- Script File Writing Example
  172
- Executing J-Link Script Files
  172
- Command Strings
  174
- List of Available Commands
  174
- Using Command Strings
  179
- Switching off CPU Clock During Debug
  181
- Cache Handling
  182
- Cache Coherency
  182
- Cache Clean Area
  182
- Cache Handling of ARM7 Cores
  182
- Cache Handling of ARM9 Cores
  182
- Virtual COM Port (VCOM)
  183
- Configuring Virtual COM Port
  183

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Segger J-Trace User Manual

Segger J-Trace User Manual (321 pages)

Brand: Segger | Category: Microcontrollers | Size: 3 MB

Table of Contents

About this Document
13
Introduction
21
J-Link / J-Trace Models
24
Model Comparison
25
Additional Features
26
Specifications
26
Hardware Versions
27
J-Link ULTRA
29
J-Link Lite Cortex-M
32
Download Speed
35
Flasher ARM
38
J-Link Coldfire
39
Common Features of the J-Link Product Family
40
Supported CPU Cores
41
Built-In Intelligence for Supported CPU-Cores
42
Intelligence in the J-Link Firmware
42
Intelligence on the PC-Side (DLL)
42
Firmware Intelligence Per Model
44
Current Models
44
Older Models
45
Supported Ides
46
Licensing
47
License Types
49
Built-In License
49
Key-Based License
49
Legal Use of SEGGER J-Link Software
50
Original SEGGER Products
51
J-Trace for Cortex-M
53
Flasher PPC
55
J-Link OEM Versions
56
Analog Devices: Midaslink
56
Atmel: SAM-ICE
56
Digi: JTAG Link
57
IAR: J-Link / J-Link KS
57
IAR: J-Link Lite
57
NXP: J-Link Lite LPC Edition
58
Illegal Clones
60
J-Link Software and Documenta- Tion Package
61
Software Overview
62
J-Link Commander (Command Line Tool)
63
Command Line Options
63
Using Command Files
64
J-Link GDB Server
66
Debugging with J-Link GDB Server
67
SEGGER-Specific GDB Protocol Extensions
83
J-Link Remote Server
96
List of Available Commands
96
Tunneling Mode
97
J-Mem Memory Viewer
100
J-Link SWO Viewer
102
Configure SWO Output after Device Reset
105
SWO Analyzer
108
Jtagload (Command Line Tool)
109
J-Link RDI (Remote Debug Interface)
110
Flash Download and Flash Breakpoints
110
Processor Specific Tools
111
J-Link Str91X Commander (Command Line Tool)
111
J-Link STM32 Unlock (Command Line Tool)
112
J-Link Software Developer Kit (SDK)
114
Installing the J-Link Software and Documentation Pack
116
Setup Procedure
116
Setting up the USB Interface
119
Uninstalling the J-Link USB Driver
120
Setting up the IP Interface
122
J-Link Configurator
125
J-Link USB Identification
127
Using the J-Link DLL
129
Updating the DLL in Third-Party Programs
129
Determining the Version of Jlink DLL
130
Determining Which DLL Is Used by a Program
130
Connecting the Target System
134
Power-On Sequence
134
Verifying Target Device Connection
134
Input Indicator
137
Output Indicator
137
Jtag Interface
138
Multiple Devices in the Scan Chain
138
Sample Configuration Dialog Boxes
138
Determining Values for Scan Chain Configuration
141
JTAG Speed
142
SWD Interface
143
SWD Speed
143
How Multi-Core Debugging Works
145
Using Multi-Core Debugging in Detail
146
Things You Should be Aware of
147
Connecting Multiple J-Links / J-Traces to Your PC
149
How Does It Work
149
J-Link Control Panel
151
Reset Strategies
157
Strategies for ARM 7/9 Devices
157
Strategies for Cortex-M Devices
159
Using DCC for Memory Access
162
What Is Required
162
Target DCC Abort Handler
162
J-Link Script Files
163

Segger J-Trace User Manual

Segger J-Trace User Manual (224 pages)

JTAG emulators for ARM Cores

Brand: Segger | Category: Controller | Size: 2 MB

Table of Contents

Table of Contents
13
1 Introduction

19
- Requirements
  20
- Supported os
  21
- J-Link / J-Trace Models
  22
- Model Comparison
  23
- J-Link ARM
  24
- J-Link Ultra
  27
- J-Link ARM Pro
  28
- J-Link ARM Lite
  29
- J-Link Lite Cortex-M
  30
- J-Trace ARM
  32
- J-Trace for Cortex-M
  34
- Flasher ARM
  36
- J-Link Coldfire
  37
- Common Features of the J-Link Product Family
  38
- Supported CPU Cores
  39
- Built-In Intelligence for Supported CPU-Cores
  40
- Intelligence in the J-Link Firmware
  40
- Intelligence on the PC-Side (DLL)
  40
- Firmware Intelligence Per Model
  43
- Supported Ides
  45
2 Licensing

47
- Introduction
  48
- Software Components Requiring a License
  49
- License Types
  50
- Built-In License
  50
- Key-Based License
  50
- Device-Based License
  51
- Legal Use of SEGGER J-Link Software
  53
- Use of the Software with 3Rd Party Tools
  53
- Original SEGGER Products
  54
- J-Link
  54
- J-Link Ultra
  54
- J-Link Pro
  55
- J-Trace
  55
- J-Trace for Cortex-M
  56
- Flasher ARM
  56
- J-Link OEM Versions
  57
- Analog Devices: Midaslink
  57
- Atmel: SAM-ICE
  57
- Digi: JTAG Link
  58
- IAR: J-Link / J-Link KS
  58
- IAR: J-Link Lite
  58
- IAR: J-Trace
  59
- NXP: J-Link Lite LPC Edition
  59
- SEGGER: J-Link Lite
  59
- J-Link Obs
  60
- Illegal Clones
  61
3 Setup

63
4 Link and J-Trace Related Software

77
5 Working with J-Link and J-Trace

95
- Connecting the Target System
  96
- Power-On Sequence
  96
- Verifying Target Device Connection
  96
- Problems
  96
- Indicators
  97
- Main Indicator
  97
- Input Indicator
  99
- Output Indicator
  99
- JTAG Interface
  100
- Multiple Devices in the Scan Chain
  100
- Sample Configuration Dialog Boxes
  100
- Determining Values for Scan Chain Configuration
  103
- JTAG Speed
  104
- SWD Interface
  105
- SWD Speed
  105
- Swo
  105
- Multi-Core Debugging
  107
- How Multi-Core Debugging Works
  107
- Using Multi-Core Debugging in Detail
  108
- Things You Should be Aware of
  109
- Connecting Multiple J-Links / J-Traces to Your PC
  111
- How Does It Work
  111
- Configuring Multiple J-Links / J-Traces
  112
- Connecting to a J-Link / J-Trace with Non Default USB-Address
  113
- J-Link Control Panel
  114
- Tabs
  114
- Reset Strategies
  120
- Strategies for ARM 7/9 Devices
  120
- Strategies for Cortex-M Devices
  122
- Using DCC for Memory Access
  124
- What Is Required
  124
- Target DCC Handler
  124
- Target DCC Abort Handler
  124
- J-Link Script Files
  125
- Actions that Can be Customized
  125
- Script File API Functions
  125
- Global DLL Variables
  128
- Global DLL Constants
  130
- Script File Language
  131
- Executing J-Link Script Files
  132
- Command Strings
  133
- List of Available Commands
  133
- Using Command Strings
  139
- Switching off CPU Clock During Debug
  141
- Cache Handling
  142
- Cache Coherency
  142
- Cache Clean Area
  142
- Cache Handling of ARM7 Cores
  142
- Cache Handling of ARM9 Cores
  142

Segger J-Trace User Manual

Segger J-Trace User Manual (206 pages)

JTAG emulators for ARM Cores

Brand: Segger | Category: Terminal Emulator | Size: 1 MB

Table of Contents

Table of Contents
11
1 Introduction

17
- J-Link / J-Trace Models
  18
- Comparison Chart
  20
- J-Link ARM
  20
- J-Link ARM Pro
  23
- J-Trace ARM
  24
- Flasher ARM
  25
- J-Link Coldfire
  25
- J-Trace for Cortex-M3
  26
- Common Features of the J-Link Product Family
  27
- Supported ARM Cores
  28
- Upcoming Supported Cores
  28
- Requirements
  29
2 Licensing

31
- Introduction
  32
- Software Components Requiring a License
  33
- License Types
  34
- Built-In License
  34
- Key-Based License
  34
- Device-Based License
  35
- Legal Use of SEGGER J-Link Software
  37
- Use of the Software with 3Rd Party Tools
  37
- Original SEGGER Products
  38
- J-Link
  38
- J-Link Pro
  38
- J-Trace
  39
- Flasher ARM
  39
- J-Link OEM Versions
  40
- Midaslink (Analog Devices)
  40
- SAM-ICE (Atmel)
  40
- Digi JTAG Link (Digi International)
  41
- IAR J-Link / IAR J-Link KS (IAR)
  41
- IAR J-Trace
  42
- J-Link Obs
  43
- Illegal Clones
  44
3 Setup

45
4 Link and J-Trace Related Software

57
5 Working with J-Link and J-Trace

75
- Connecting the Target System
  76
- Power-On Sequence
  76
- Verifying Target Device Connection
  76
- Problems
  76
- Indicators
  77
- Main Indicator
  77
- Input Indicator
  79
- Output Indicator
  79
- JTAG Interface
  80
- Multiple Devices in the Scan Chain
  80
- Sample Configuration Dialog Boxes
  80
- Determining Values for Scan Chain Configuration
  83
- JTAG Speed
  84
- SWD Interface
  85
- Swo
  85
- Multi-Core Debugging
  87
- How Multi-Core Debugging Works
  87
- Using Multi-Core Debugging in Detail
  88
- Things You Should be Aware of
  89
- Connecting Multiple J-Links / J-Traces to Your PC
  91
- How Does It Work
  91
- Configuring Multiple J-Links / J-Traces
  92
- Connecting to a J-Link / J-Trace with Non Default USB-Address
  93
- J-Link Control Panel
  94
- Tabs
  94
- Reset Strategies
  100
- Strategies for ARM 7/9 Devices
  100
- Strategies for Cortex-M3 Devices
  102
- Using DCC for Memory Access
  103
- What Is Required
  103
- Target DCC Handler
  103
- Target DCC Abort Handler
  103
- Command Strings
  104
- List of Available Commands
  104
- Using Command Strings
  110
- Switching off CPU Clock During Debug
  112
- Cache Handling
  113
- Cache Coherency
  113
- Cache Clean Area
  113
- Cache Handling of ARM7 Cores
  113
- Cache Handling of ARM9 Cores
  113

Segger J-Trace User Manual

Segger J-Trace User Manual (122 pages)

JTAG Emulators for ARM Cores

Brand: Segger | Category: Adapter | Size: 1 MB

Table of Contents

Table of Contents
7
1 Introduction

11
- J-Link Overview
  12
- Features of J-Link
  12
- J-Trace Overview
  13
- Features of J-Trace
  13
- Test Environment
  14
- Specifications
  15
- Specifications for J-Link
  15
- Specifications for J-Trace
  15
- Download Speed
  16
- Requirements
  17
2 Setup

19
- Installing the J-Link ARM Software and Documen-Tation Pack
  20
- Setup Procedure
  21
- Verifying Correct Driver Installation
  24
- Uninstalling the J-Link USB Driver
  26
- Connecting the Target System
  27
- Power-On Sequence
  27
- Verifying Target Device Connection
  27
- Problems
  27
- Scan Chain Configuration
  28
- Sample Configuration Dialog Boxes
  28
- Determining Values for Scan Chain Configuration
  30
- JTAG Speed
  31
- Fixed JTAG Speed
  31
- Automatic JTAG Speed
  31
- Adaptive Clocking
  31
3 Link and J-Trace Related Software

33
4 Working with J-Link and J-Trace

45
- Supported ARM Cores
  46
- Reset Strategies
  47
- Reset Strategies in Detail
  47
- Cache Handling
  49
- Cache Coherency
  49
- Cache Clean Area
  49
- Cache Handling of ARM7 Cores
  49
- Cache Handling of ARM9 Cores
  49
- Connecting Multiple J-Links / J-Traces to Your PC
  50
- How Does It Work
  50
- Configuring Multiple J-Links / J-Traces
  51
- Connecting to a J-Link / J-Trace with Non Default USB-Address
  52
- Multi-Core Debugging
  53
- How Multi-Core Debugging Works
  53
- Using Multi-Core Debugging in Detail
  54
- Things You Should be Aware of
  56
- Multiple Devices in the Scan Chain
  57
- Configuration
  57
- Using DCC for Memory Access
  58
- What Is Required
  58
- Target DCC Handler
  58
- Target DCC Abort Handler
  58
- Testing DCC Memory Access
  59
- Command Strings
  60
- List of Available Commands
  60
- Using Command Strings
  64
- Switching off CPU Clock During Debug
  66

Segger J-Trace User Manual

Segger J-Trace User Manual (4 pages)

Brand: Segger | Category: Microcontrollers | Size: 0 MB

Table of Contents

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