Page 1 J-Link / J-Trace User guide of the JTAG emulators for ARM Cores Manual Rev. 73 Date: July 3, 2009 Document: UM08001 A product of SEGGER Microcontroller GmbH & Co. KG www.segger.com...
Page 2 Please make sure your manual is the latest edition. While the information herein is assumed to be accurate, SEGGER Microcontroller GmbH & Co. KG (the manufacturer) assumes no responsibility for any errors or omissions. The manufacturer makes and you receive no warranties or conditions, express, implied, statutory or in any communication with you.
Page 3 For further information on topics or routines not yet specified, please contact us. Revision Date Explanation Chapter "Introduction" * Section "J-Link and J-Trace models" added * Sections "Model comparison chart" & "J-Link bundle comparison chart"added Chapter "J-Link and J-Trace models" removed 090701 Chapter "Hardware"...
Page 4 090108 updated. * Section "Target board design for SWD" added. Chapter "Working with J-Link Pro" 090105 * Section "Connecting J-Link Pro the first time" updated. Chapter "Working with J-Link Pro" * Section "Introduction" updated. * Section "Configuring J-Link Pro 081222 via web interface"...
Page 5 Revision Date Explanation Chapter "Flash download and flash breakpoints" updated. 080630 Chapter "J-Link status window" renamed to "J-Link control panel" Various corrections. Chapter "Flash download and flash breakpoints" Section "Licensing" updated. 080627 Section "Using flash download and flash breakpoints with different debuggers" updated.
Page 6 070312 "Differences between different versions" supplemented. Chapter "J-Link / J-Trace related software": 070307 "J-Link GDB Server" licensing updated. Chapter "J-Link / J-Trace related software" updated and reorganized. 070226 Chapter "Hardware" "List of OEM products" updated Chapter "Device specifics" added 070221 Subchapter "Command strings"...
Page 7 060117 Screenshots updated. 051208 Chapter Working with J-Link: Sketch added. Chapter Working with J-Link: "Connecting multiple J-Links to your PC" added. Chapter Working with J-Link: "Multi core debug- 051118 ging" added. Chapter Background information: "J-Link firm- ware" added. 051103 Chapter Setup: "JTAG Speed" added.
Page 9 For simplicity, we will refer to J-Link ARM as J-Link in this manual. For simplicity, we will refer to J-Link ARM Pro as J-Link Pro in this manual. Typographic conventions This manual uses the following typographic conventions:...
Page 10 Apart from its main focus on software tools, SEGGER develops and produces programming tools for flash microcontrollers, as well as J-Link, a JTAG emulator to assist in develop- ment, debugging and production, which has rapidly become the industry standard for debug access to ARM cores.
Page 11: Table Of Contents
2.6.5 IAR J-Trace..................... 40 J-Link OBs ....................41 Illegal Clones ..................42 3 Setup..........................43 Installing the J-Link ARM software and documentation pack ......44 3.1.1 Setup procedure..................44 Setting up the USB interface ..............47 3.2.1 Verifying correct driver installation ............. 47 Uninstalling the J-Link USB driver ..............
Page 12 5.6.1 How does it work? ................... 89 5.6.2 Configuring multiple J-Links / J-Traces ............90 5.6.3 Connecting to a J-Link / J-Trace with non default USB-Address...... 91 J-Link control panel ................. 92 5.7.1 Tabs...................... 92 Reset strategies ..................98 5.8.1 Strategies for ARM 7/9 devices ..............
Page 13 Pinout for JTAG ..................148 8.1.2 Pinout for SWD..................150 38-pin Mictor JTAG and Trace connector ........... 153 8.2.1 Connecting the target board..............153 8.2.2 Pinout ....................154 J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 14 Code tracing and data tracing ..............173 9.4.3 J-Trace integration example - IAR EWARM ..........173 Embedded Trace Buffer (ETB) ..............177 Flash programming ................178 9.6.1 How does flash programming via J-Link / J-Trace work? ......178 9.6.2 Data download to RAM ................178 9.6.3 Data download via DCC................178 9.6.4 Available options for flash programming ............178...
Page 15 13 Literature and references...................201 J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 17: Introduction
Chapter 1 Introduction This chapter gives a short overview about J-Link and J-Trace. J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 18: J-Link / J-Trace Models
J-Links / J-Traces have the hardware version printed on the back label. If this is not the case with your J-Link / J-Trace, start JLink.exe. As part of the initial message, the hardware version is displayed.
Page 19 FlashDL works, please refer to Flash download and flash breakpoints on page 113. In order to use the flash breakpoints with J-Link no additional license for flash download is required. The flash breakpoint feature allows setting an unlimited num- ber of breakpoints even if the application program is not located in RAM, but in flash memory.
Page 20: Comparison Chart
RDI interface available, which allows using J-Link with RDI compliant software * = Supported by J-Link hardware version 6 ** = Measured with J-Link Rev.5, ARM7 @ 50 MHz, 12MHz JTAG speed. 1.1.3.2 Specifications* USB powered <50mA if target power is Power Supply off.
Page 21 48 MHz / n, where n is 4, 5, ..., resulting in speeds of: 12.000 MHz (n = 4) 9.600 MHz (n = 5) 8.000 MHz (n = 6) 6.857 MHz (n = 7) J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 22 5V target supply (pin 19) of Kick-Start versions of J-Link is current monitored and limited. J-Link automatically switches off 5V supply in case of over-current to protect both J-Link and host computer. Peak current (<= 10 ms) limit is 1A, operating current limit is 300mA.
Page 23: J-Link Arm Pro
• RDI interface available, which allows using J-Link with RDI compliant software ** = Measured with J-Link Pro Rev. 1.1, ARM7 @ 50 MHz, 12MHz JTAG speed. 1.1.4.2 Download speed The following table lists performance values (Kbytes/s) for writing to memory (RAM):...
Page 24: J-Trace Arm
Microsoft Windows 2000 Microsoft Windows XP Microsoft Windows XP x64 Supported OS Microsoft Windows 2003 Microsoft Windows 2003 x64 Microsoft Windows Vista Microsoft Windows Vista x64 Table 1.4: J-Trace specifications J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 25: Flasher Arm
ARM, please refer to UM08007, Flasher ARM User’s Guide. 1.1.7 J-Link ColdFire J-Link ColdFire is a BDM emulator designed for ColdFire® cores. It connects via USB to a PC running Microsoft Windows 2000, Windows XP, Windows 2003, or Windows Vista. J-Link ColdFire has a built-in 26-pin BDM connector, which is compatible to the standard 26-pin connector defined by Freescale.
Page 26: J-Trace For Cortex-M3
J-Trace for Cortex-M3 is a JTAG/SWD emulator designed for Cortex-M3 cores which includes trace (ETM) support. J-Trace for Cortex-M3 can also be used as a J-Link and it also supports ARM7/9 cores. Tracing on ARM7/9 targets is not supported. 1.1.8.1 Additional features •...
Page 27: Common Features Of The J-Link Product Family
Memory viewer (J-Mem) included • TCP/IP server included, which allows using J-Trace via TCP/IP networks • RDI interface available, which allows using J-Link with RDI compliant software • Flash programming software (J-Flash) available • Flash DLL available, which allows using flash functionality in custom applications •...
Page 28: Supported Arm Cores
Cortex-M3 1.3.1 Upcoming supported cores • Cortex-A8/A9 • Cortex-R4 • X-Scale If you need support for any of these cores you should get in touch with us (info@segger.com). J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 29: Requirements
Requirements Host System To use J-Link or J-Trace you need a host system running Windows 2000, Windows XP, Windows 2003, or Windows Vista. Target System An ARM7/ARM9/ARM11 or Cortex-M3 target system is required. The system should have a standardized 20-pin connector as defined by ARM Ltd. for a simple JTAG con- nection.
Page 31: Licensing
Chapter 2 Licensing This chapter describes the different license types of J-Link related software and the legal use of the J-Link software with original SEGGER and OEM products. J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 32: Introduction
J-Link functionality can be enhanced by the features J-Flash, RDI, flash download (J- Link ARM FlashDL) and flash breakpoints (FlashBP). These features do not come with J-Link and need additional licenses. In the following the licensing options of the software will be explained.
Page 33: Software Components Requiring A License
For more information about J-Flash licensing procedure / license types, please refer to the J-Flash User Guide (UM08003), chapter Licensing. In the following the licensing procedure and license types of J-Link ARM FlashDL and FlashBP are explained J-Link / J-Trace (UM08001)
Page 34: License Types
Key-based license This type of license is used if you already have a J-Link, but want to enhance its func- tionality by using J-Link ARM FlashDL and FlashBP. In addition to that, the key- based license is used for trial licenses.
Page 35: Device-Based License
The device-based license is a free license, available for some devices. It’s already included in J-Link, so no keys are necessary to enable this license type. To activate a device based license, the debugger needs to select a supported device.
Page 36 RDI, J-Link ARM FlashDL, J- LPC2378 Link ARM FlashBP RDI, J-Link ARM FlashDL, J- LPC2468 Link ARM FlashBP RDI, J-Link ARM FlashDL, J- LPC2478 Link ARM FlashBP Table 2.1: Device list J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 37: Legal Use Of Segger J-Link Software
Use of software SEGGER J-Link software may only be used with original SEGGER products and autho- rized OEM products. The use of the licensed software to operate SEGGER product clones is prohibited and illegal.
Page 38: Original Segger Products
CHAPTER 2 Licensing Original SEGGER products The following products are original SEGGER products for which the use of the J-Link software is allowed: 2.5.1 J-Link J-Link is a JTAG emulator designed for ARM cores. It connects via USB to a PC running Microsoft Windows 2000, Windows XP, Windows 2003 or Windows Vista.
Page 39: J-Trace
RS232 interface to a PC, running Microsoft Windows 2000, Win- dows XP, Windows 2003 or Windows Vista. Flasher ARM has a built-in 20-pin JTAG connector, which is compatible with the standard 20-pin connector defined by ARM. J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 40: J-Link Oem Versions
In any case, it should be possible to use the J-Link software with these OEM versions. How- ever, proper function cannot be guaranteed for OEM versions. SEGGER Microcontrol- ler does not support OEM versions;...
Page 41: Digi Jtag Link (Digi International)
Limitations Digi JTAG Link works with Digi devices only. This limitation can NOT be lifted; if you would like to use J-Link with a device from an other manufacturer, you need to buy a separate J-Link. Licenses License for GDB Server is included. Other licenses can be added.
Page 42: Iar J-Trace
J-Trace with Keil MDK, you need to buy a separate J-Trace. Licenses No licenses are included. All licenses can be added. J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 43: J-Link Obs
J-Link OBs J-Link OBs (J-Link On Board) are single chip versions of J-Link which are used on var- ious eval boards. It is legal to use J-Link software with these boards, provided that the eval board manufacturer has obtained a license from SEGGER. The following list shows the eval board manufacturer which are allowed to use J-Link OBs: •...
Page 44: Illegal Clones
The use of illegal J-Link clones with this software is a violation of US, European and other international laws and is prohibited. If you are in doubt if your unit may be legally used with SEGGER J-Link software, please get in touch with us.
Page 45: Setup
Chapter 3 Setup This chapter describes the setup procedure required in order to work with J-Link / J- Trace. Primarily this includes the installation of the J-Link software and documenta- tion package, which also includes a kernel mode J-Link USB driver in your host sys- tem.
Page 46: Installing The J-Link Arm Software And Documentation Pack
J-Link USB driver. Some of the applications require an additional license, free trial licenses are available upon request from www.segger.com. Refer to chapter J-Link and J-Trace related software on page 55 for an overview about the J-Link software and documentation pack. 3.1.1...
Page 47 The Choose options dialog is opened. The Create entry in start menu and the Add shortcuts to desktop option are preselected. Accept or deselect the options and confirm the selection with the Next > button. The installation process will be started. J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 48 The J-Link software and documentation pack is successfully installed on your PC. Connect your J-Link via USB with your PC. The J-Link will be identified and after a short period the J-Link LED stops rapidly flashing and stays on permanently.
Page 49: Setting Up The Usb Interface
In addition you can verify the driver installation by consulting the Windows device manager. If the driver is installed and your J-Link / J-Trace is connected to your com- puter, the device manager should list the J-Link USB driver as a node below "Univer- sal Serial Bus controllers"...
Page 50 Setup Right-click on the driver to open a context menu which contains the command Prop- erties. If you select this command, a J-Link driver Properties dialog box is opened and should report: This device is working properly. If you experience problems, refer to the chapter Support and FAQs on page 187 for help.
Page 51: Uninstalling The J-Link Usb Driver
Uninstalling the J-Link USB driver If J-Link / J-Trace is not properly recognized by Windows and therefore does not enu- merate, it make sense to uninstall the J-Link USB driver. This might be the case when: • The LED on the J-Link / J-Trace is rapidly flashing.
Page 52: Setting Up The Ip Interface
Connecting J-Link only via Ethernet and read out the IP via the DHCP IP Assign- ment table of your DHCP Server. In the following, both ways to get the IP address assigned to J-Link via DHCP, are explained. 3.4.1.1 Connecting via USB and Ethernet When using JLink.exe in order to read out the IP address, J-Link has to be con-...
Page 53: Configuring The J-Link
By default, J-Link is configured to receive an IP address and a subnet mask via DHCP. It is also possible to assign a fixed IP address to it. Setting up J-Link can be done via JLink.exe or via web interface. In the following, both configuration methods are described.
Page 54 Setup Assigning an IP address manually If you do not want J-Link to be configured via DHCP, you can assign an IP address and a subnet mask (optional) manually. This is done via the ipaddr command in JLink.exe. This command can be used in four different ways, which are explained in...
Page 55: Faqs
3.4.3 FAQs How can I use J-Link with GDB and Ethernet? You have to use the J-Link ARM GDB Server in order to connect to J-Link via GDB and Ethernet. J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 57: Link And J-Trace Related Software
This chapter describes Segger’s J-Link / J-Trace related software portfolio, which cov- ers nearly all phases of the development of embedded applications. The support of the remote debug interface (RDI) and the J-Link GDBServer allows an easy J-Link integration in all relevant toolchains.
Page 58: J-Link Related Software
J-Link and J-Trace related software J-Link related software 4.1.1 J-Link software and documentation package J-Link is shipped with a bundle of applications. Some of the applications require an additional license, free trial licenses are available upon request from www.seg- ger.com. Software Description JLinkARM.dll...
Page 59: List Of Additional Software Packages
Command line tool that opens an svf file and sends the data in JTAGLoad it via J-Link / J-Trace to the target. J-Link Software The J-Link Software Developer Kit is needed if you want to Developer Kit write your own program with J-Link / J-Trace. (SDK) J-Link Flash Soft- An enhanced version of the JLinkARM.DLL, which contains...
Page 60: J-Link Software And Documentation Package In Detail
4.2.1 J-Link Commander (Command line tool) J-Link Commander (JLink.exe) is a tool that can be used for verifying proper instal- lation of the USB driver and to verify the connection to the ARM chip, as well as for simple analysis of the target system. It permits some simple commands, such as memory dump, halt, step, go and ID-check, as well as some more in-depths analysis of the state of the ARM core and the ICE breaker module.
Page 61: J-Link Str91X Commander (Command Line Tool)
4.2.2 J-Link STR91x Commander (Command line tool) J-Link STR91x Commander (JLinkSTR91x.exe) is a tool that can be used to configure STR91x cores. It permits some STR9 specific commands like: • Set the configuration register to boot from bank 0 or 1 •...
Page 62: J-Link Stm32 Commander (Command Line Tool)
4.2.3 J-Link STM32 Commander (Command line tool) J-Link STM32 Commander (JLinkSTM32.exe) is a free command line tool which can be used to disable the hardware watchdog of STM32 devices which can be activated by programming the option bytes. Moreover the J-Link STM32 Commander unsecures a read-protected STM32 device by re-programming the option bytes.
Page 63: J-Link Tcp/Ip Server (Remote J-Link / J-Trace Use)
The J-Link TCP/IP Server allows using J-Link / J-Trace remotely via TCP/IP. This enables you to connect to and fully use a J-Link / J-Trace from another computer. Performance is just slightly (about 10%) lower than with direct USB connection.
Page 64: J-Mem Memory Viewer
SFRs can be written. You can choose between 8/16/32-bit size for read and write accesses. J-Mem works nicely when modifying SFRs, especially because it writes the SFR only after the complete value has been entered. J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 65: J-Flash Arm (Program Flash Memory Via Jtag)
However, to actually program devices via J-Flash ARM and J-Link / J-Trace you are required to obtain a license key from us. Evaluation licenses are available free of charge. For further information go to our website or contact us directly.
Page 66: J-Link Rdi (Remote Debug Interface)
The J-Link RDI software is an remote debug interface for J-Link. It makes it possible to use J-Link with any RDI compliant debugger. The main part of the software is an RDI-compliant DLL, which needs to be selected in the debugger. There are two addi- tional features available which build on the RDI software foundation.
Page 67: J-Link Gdb Server
GDB is freely available from the GNU committee under: http://www.gnu.org/software/gdb/download/ J-Link GDB Server is distributed as "free for evaluation and non commercial use". The software can be used free of charge for educational and nonprofit purposes without additional license.
Page 68: Dedicated Flash Programming Utilities For J-Link
If you want to use the dedicated flash programming utilities for commercial and production pur- poses, you need to obtain a license from SEGGER. SEGGER also offers to create ded- icated flash programming utilities for custom hardware. When starting a dedicated...
Page 69: Supported Flash Memories
If you want to use dedicated flash programming utilities for production and commer- cial purposes you need to obtain a license from SEGGER. In order to obtain a license for a dedicated flash programming utility, there are two options: •...
Page 70: F.a.q
Q: I want to use the dedicated flash programming utilities with my own hardware. Is that possible? A: The free dedicated flash programming utilities which come with J-Link do not support custom hardware.mIn order to use your own hardware with a dedicated...
Page 71: Additional Software Packages In Detail
The J-Link Software Developer Kit is needed if you want to write your own program with J-Link / J-Trace. The J-Link DLL is a standard Windows DLL typically used from C programs (Visual Basic or Delphi projects are also possible). It makes the entire...
Page 72: Using The J-Linkarm.dll
Determining which DLL is used by a program on page 71. J-Link DLL updater The J-Link DLL updater is a tool which comes with the J-Link software and allows the user to update the JLinkARM.dll in all installations of the IAR Embedded Work- bench, in a simple way.
Page 73: Determining The Version Of Jlinkarm.dll
Process Explorer. It shows you details about the DLLs, used by your program, such as manufacturer and version. Process Explorer is - at the time of writing - a free utility which can be downloaded from www.sysinternals.com. J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 74 CHAPTER 4 J-Link and J-Trace related software J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 75: Working With J-Link And J-Trace
Chapter 5 Working with J-Link and J-Trace This chapter describes functionality and how to use J-Link and J-Trace. J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 76: Connecting The Target System
5.1.2 Verifying target device connection If the USB driver is working properly and your J-Link / J-Trace is connected with the host system, you may connect J-Link / J-Trace to your target hardware. Then start JLink.exe which should now display the normal J-Link / J-Trace related information and in addition to that it should report that it found a JTAG target and the target’s...
Page 77: Indicators
5.2.1 Main indicator For J-Links up to V7, the main indicator is single color (Green). J-Link V8 comes with a bi-color indicator (Green & Red LED), which can show multiple colors: green, red and orange.
Page 78 GREEN, constant Emulator has enumerated and is in Idle mode. GREEN, switched off for J-Link heart beat. Will be activated after the emulator 10ms once per second has been in idle mode for at least 7 seconds. Emulator has a fatal error. This should not normally hap- GREEN, flashing at 1 Hz pen.
Page 79: Input Indicator
5.2.2 Input indicator Some newer J-Links such as the J-Link PRO come with additional input/output Indica- tors. The input indicator is used to give the user some information about the status of the target hardware. 5.2.2.1 Bi-color input indicator Indicator status...
Page 80: Jtag Interface
IAR C-SPY® debugger, ARM’s AXD using RDI, a flash programming appli- cation such as SEGGER’s J-Flash, or any other application using J-Link / J-Trace. It is the application’s responsibility to supply a way to configure the scan chain. Most applications offer a dialog box for this purpose.
Page 81 SEGGER J-Flash configuration dialog This dialog box can be found at Options|Project settings. J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 82 This dialog can be found under RDI|Configure for example in IAR Embedded Work- bench®. For detailed information check the IAR Embedded Workbench user guide. IAR J-Link configuration dialog box This dialog can be found under Project|Options. J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 83: Determining Values For Scan Chain Configuration
If only one device is connected to the scan chain, the default configuration can be used. In other cases, J-Link / J-Trace may succeed in automatically recognizing the devices on the scan chain, but whether this is possible depends on the devices present on the scan chain.
Page 84: Jtag Speed
JTAG interface. If you use the adaptive clocking feature, transmission delays, gate delays, and syn- chronization requirements result in a lower maximum clock frequency than with non- adaptive clocking. J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 85: Swd Interface
Table 5.6: J-Link supported SWO input speeds 5.4.1.2 Configuring SWO speeds The max. SWO speed in practice is the max. speed which both, target and J-Link can handle. J-Link can handle the frequencies described in SWO on page 83 whereas the max.
Page 86 Example 2 Target CPU running at 10 MHz. Possible SWO output speeds are: 10MHz, 5MHz, 3.33MHz, ... J-Link V7: Supported SWO input speeds are: 6MHz / n, n>= 1: 6MHz, 3MHz, 2MHz, 1.5MHz, ... Permitted combinations are: SWO output SWO input...
Page 87: Multi-Core Debugging
Multi-core debugging J-Link / J-Trace is able to debug multiple cores on one target system connected to the same scan chain. Configuring and using this feature is described in this section. 5.5.1 How multi-core debugging works Multi-core debugging requires multiple debuggers or multiple instances of the same debugger.
Page 88: Using Multi-Core Debugging In Detail
Working with J-Link and J-Trace 5.5.2 Using multi-core debugging in detail Connect your target to J-Link / J-Trace. Start your debugger, for example IAR Embedded Workbench for ARM. Choose Project|Options and configure your scan chain. The picture below shows the configuration for the first ARM core on your target.
Page 89: Things You Should Be Aware Of
JTAG speeds. For example: Core #1: 2MHz maximum JTAG speed Core #2: 4MHz maximum JTAG speed Scan chain: 2MHz maximum JTAG speed J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 90 All cores share the same RESET line. You should be aware that resetting one core through the RESET line means resetting all cores which have their RESET pins con- nected to the RESET line on the target. J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 91: Connecting Multiple J-Links / J-Traces To Your Pc
The product id (PID) for J-Link / J-Trace #2 is 102 and so on. A different PID means that J-Link / J-Trace is identified as a different device, requir- ing a new driver. The driver for a new J-Link device will be installed automatically.
Page 92: Configuring Multiple J-Links / J-Traces
12. you can verify the driver installation by consulting the Windows device manager. If the driver is installed and your J-Link / J-Trace is connected to your computer, the device manager should list the J-Link USB drivers as a node below "Universal Serial Bus controllers"...
Page 93: Connecting To A J-Link / J-Trace With Non Default Usb-Address
Connecting to a J-Link / J-Trace with non default USB- Address Restart JLink.exe and type usb 1 to connect to J-Link / J-Trace #1. You may connect other J-Links / J-Traces to your PC and connect to them as well. To connect to an unconfigured J-Link / J-Trace (with default address "0"), restart...
Page 94: J-Link Control Panel
J-Link features such as J-Link ARM FlashDL, FlashBP and ARM instruction set simulation. The J-Link control panel win- dow can be accessed via the J-Link tray icon in the tray icon list. This icon is available when the debug session is started.
Page 95 Save settings, otherwise they are lost when the debug session is closed. Section: Flash download In this section, settings for the use of the J-Link ARM FlashDL feature and related settings can be configured. When a license for J-Link ARM FlashDL is found, the color indicator is green and "License found"...
Page 96 Save settings: When this button is pushed, the current settings in the Settings tab will be saved in a configuration file. This file is created by J-Link and will be created for each project and each project configuration (e.g. Debug_RAM, Debug_Flash).
Page 97 Note: It is possible for the debugger to bypass the breakpoint functionality of the J-Link software by writing to the debug registers directly. This means for ARM7/ ARM9 cores write accesses to the ICE registers, for Cortex-M3 devices write accesses to the memory mapped flash breakpoint registers and in general simple write accesses for software breakpoints (if the program is located in RAM).
Page 98 In this section the name and the value of the CPU registers are shown. 5.7.1.6 Target Power In this section currently just the power consumption of the target hardware is shown. J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 99 In this section SWV information are shown. • Status: Shows the encoding and the baudrate of the SWV data received by the target (Manchester/UART, currently J-Link only supports UART encoding). • Bytes in buffer: Shows how many bytes are in the DLL SWV data buffer.
Page 100: Reset Strategies
Some CPUs can actually be halted before executing any instruction, because the start of the CPU is delayed after reset release. If a pause has been specified, J-Link waits for the specified time before trying to halt the CPU. This can be useful if a bootloader which resides in flash or ROM needs to be started after reset.
Page 101 No reset is performed. Nothing happens. 5.8.1.5 Type 4: Hardware, halt with WP The hardware RESET pin is used to reset the CPU. After reset release, J-Link continu- ously tries to halt the CPU using a watchpoint. This typically halts the CPU shortly after reset release;...
Page 102: Strategies For Cortex-M3 Devices
5.8.2.3 Type 2: ResetPin J-Link pulls its RESET pin low to reset the core and the peripherals. This normally causes the CPU RESET pin of the target device to go low as well, resulting in a reset of both CPU and peripherals.
Page 103: Using Dcc For Memory Access
This DCC handler typically requires less than 1 µs per call. The DCC handler, as well as the optional DCC abort handler, is part of the J-Link soft- ware package and can be found in the "Samples\DCC\IAR" directory of the package.
Page 104: Command Strings
Working with J-Link and J-Trace 5.10 Command strings The behavior of the J-Link can be customized via command strings passed to the JLinkARM.dll which controls J-Link. Applications such as the J-Link Commander, but also the C-SPY debugger which is part of the IAR Embedded Workbench, allow pass- ing one or more command strings.
Page 105 To avoid stalling the debug session, a critical memory area can be excluded from access: J-Link will not try to read or write to critical memory areas and instead ignore the access silently. Some debuggers (such as IAR C-SPY) can try to access J-Link / J-Trace (UM08001) ©...
Page 106 0x40008000-0x7FCFFFFF Reserved 0x7FD02000-0x7FD02000 Reserved 0x80000000-0xDFFFFFFF Reserved To exclude these areas from being accessed through J-Link the map exclude com- mand should be used as follows: map exclude 0x00080000-0x3FFFFFFF map exclude 0x40008000-0x7FCFFFFF map exclude 0x7FD02000-0x7FD02000 map exclude 0x80000000-0xDFFFFFFF 5.10.1.7 map indirectread This command can be used to read a memory area indirectly.
Page 107 Note that if this check is turned off (SetCheckModeAfterRead = 0), the success of read operations cannot be verified anymore and possible data aborts are not recognized. J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 108 SetResetType = <value> Example SetResetType = 0 5.10.1.14SetRestartOnClose This command specifies whether the J-Link restarts target execution on close. The default is to restart target execution. This can be disabled by using this command. Syntax SetRestartOnClose = 0 | 1...
Page 109 SetDbgPowerDownOnClose = 0 // Disables debug power-down on close. 5.10.1.16SetSysPowerDownOnIdle When using this command, the target CPU is powered-down when no transmission between J-Link and the target CPU was performed for a specific time. When the next command is given, the CPU is powered-up. Note: This command works only for Cortex-M3 devices.
Page 110: Using Command Strings
Example SupplyPowerDefault = 1 5.10.2 Using command strings 5.10.2.1 J-Link Commander The J-Link command strings can be tested with the J-Link Commander. Use the com- mand exec supplemented by one of the command strings. Example exec SupplyPower = 1 exec map reset exec map exclude 0x10000000-0x3FFFFFFF 5.10.2.2 IAR Embedded Workbench...
Page 111 On the Extra Options page, select Use command line options. Enter --jlink_exec_command "<CommandLineOption>" in the textfield, as shown in the screenshot below. If more than one command should be used separate the com- mands with semicolon. J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 112: Switching Off Cpu Clock During Debug
In this case, the CPU will stop at the first instruction in the ISR (typically at address 0x18). J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 113: Cache Handling
Because ARM7 cores have a unified cache, there is no need to handle the caches dur- ing debug. 5.12.4 Cache handling of ARM9 cores ARM9 cores with cache require J-Link / J-Trace to handle the caches during debug. If the processor enters debug state with caches enabled, J-Link / J-Trace does the fol- lowing:...
Page 114 CHAPTER 5 Working with J-Link and J-Trace J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 115: Flash Download And Flash Breakpoints
Chapter 6 Flash download and flash break- points This chapter describes how flash download and flash breakpoints with J-Link work. In addition to that it contains a list of supported microcontrollers for J-Link. J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 116: Introduction
RDI software, until now. Both features require an additional license. For more information about flash download and flash breakpoints, please refer to J-Link RDI User’s Guide (UM08004), chapter Flash download and chapter Breakpoints in flash memory.
Page 117: Licensing
ARM FlashDL) or flash breakpoints (FlashBP), but the standard J-Link does not come with a built-in license. You will need to obtain a license for every J-Link. For more information about the different license types, please refer to License types on page 32.
Page 118 Flash download and flash breakpoints Now choose Add license to add one or more new licenses. Enter your license(s) and choose OK. Now the licenses should have been added. J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 119: Supported Devices
It is customer’s responsibility to make sure that the device he wants to use flash programming with is supported. In case of doubt, you should con- tact SEGGER and ask for a trial license. The device is selected by its device identifier.
Page 120 Luminary LM3S812 LM3S812 Luminary LM3S815 LM3S815 Luminary LM3S817 LM3S817 Luminary LM3S818 LM3S818 Luminary LM3S828 LM3S828 Luminary LM3S2110 LM3S2110 Luminary LM3S2139 LM3S2139 Luminary LM3S2410 LM3S2410 Table 6.1: Supported microcontrollers J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 121 LPC1766 NXP** LPC1768 LPC1768 LPC2101 LPC2101 LPC2102 LPC2102 LPC2103 LPC2103 LPC2104 LPC2104 LPC2105 LPC2105 LPC2106 LPC2106 LPC2109 LPC2109 LPC2114 LPC2114 LPC2119 LPC2119 LPC2124 LPC2124 Table 6.1: Supported microcontrollers J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 122 ML67Q4060 ML67Q4061 ML67Q4061 Samsung* S3F445HX S3F445HX STM32F101C6 STM32F101C6 STM32F101C8 STM32F101C8 STM32F101CB STM32F101CB STM32F101R6 STM32F101R6 STM32F101R8 STM32F101R8 STM32F101RB STM32F101RB STM32F101RC STM32F101RC STM32F101RD STM32F101RD STM32F101RE STM32F101RE Table 6.1: Supported microcontrollers J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 123 STR712FR1 STR712FR1 STR712FR2 STR712FR2 STR715FR0 STR715FR0 STR730FZ1 STR730FZ1 STR730FZ2 STR730FZ2 STR731FV0 STR731FV0 STR731FV1 STR731FV1 STR731FV2 STR731FV2 STR735FZ1 STR735FZ1 STR735FZ2 STR735FZ2 STR736FV0 STR736FV0 STR736FV1 STR736FV1 Table 6.1: Supported microcontrollers J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 124 STR912FAZ42 STR912FAZ42 STR912FAZ44 STR912FAZ44 STR912FAZ46 STR912FAZ46 STR912FAZ47 STR912FAZ47 STR912FM32 STR912FM32 STR912FM42 STR912FM42 STR912FM44 STR912FM44 STR912FW32 STR912FW32 STR912FW42 STR912FW42 STR912FW44 STR912FW44 TMS470R1A64 TMS470R1A64 TMS470R1A128 TMS470R1A128 Table 6.1: Supported microcontrollers J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 125 TMS470R1B512 TMS470R1B768 TMS470R1B768 TMS470R1B1M TMS470R1B1M TMS470R1VF288 TMS470R1VF288 TMS470R1VF688 TMS470R1VF688 TMS470R1VF689 TMS470R1VF689 Toshiba** TMPM330FDFG TMPM330FDFG Table 6.1: Supported microcontrollers *Supported by J-Flash only. **Not supported by J-Link ARM RDI J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 126: Using Flash Download And Flash Breakpoints With Different Debuggers
First, choose the right device in the project settings if not already done. The device settings can be found at Project->Options->General Options->Target. To use J-Link ARM FlashDL the IAR flashloader has to be disabled (the FlashBP fea- ture can also be used when IAR flashloader is enabled). To disable the IAR flashlo- ader the checkbox Use flash loader(s) at Project->Options->Debugger-...
Page 127: Keil Mdk
If you use the IAR project for the first time, the use of J-Link ARM FlashDL and FlashBPs is set to Auto, which is the default value. For more information about dif- ferent configurations for J-Link ARM FlashDL and FlashBPs please refer to Settings on page 93.
Page 128 CHAPTER 6 Flash download and flash breakpoints Then J-Link / J-Trace has to be selected as debugger. To select J-Link / J-Trace as debugger simply choose J-Link / J-Trace from the list box which can be found at Project->Options for Target->Debug.
Page 129: J-Link Gdb Server
6.4.3 J-Link GDB Server The configuration for the J-Link GDB Server is done by the .gdbinit file. The follow- ing commands has to be added to the .gdbinit file to enable J-Link ARM FlashDL and FlashBPs: monitor flash device <DeviceID>...
Page 130 CHAPTER 6 Flash download and flash breakpoints J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 131: Device Specifics
Chapter 7 Device specifics This chapter gives some additional information about specific devices. J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 132: Analog Devices
CHAPTER 7 Device specifics Analog Devices J-Link has been tested with the following MCUs from Analog Devices, but should work with any ARM7/9 and Cortex-M3 device: • ADuC7020x62 • ADuC7020x62 • ADuC7021x32 • ADuC7021x32 • ADuC7021x62 • ADuC7021x62 • ADuC7022x32 •...
Page 133 Analog ADuC7025x62 • Analog ADuC7026x62 • Analog ADuC7027x62 • Analog ADuC7030 • Analog ADuC7031 • Analog ADuC7032 • Analog ADuC7033 • Analog ADuC7128 • Analog ADuC7129 • Analog ADuC7229x126 J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 134: Atmel
CHAPTER 7 Device specifics ATMEL J-Link has been tested with the following ATMEL devices, but should work with any ARM7/9 and Cortex-M3 device: • AT91SAM7A3 • AT91SAM7S32 • AT91SAM7S321 • AT91SAM7S64 • AT91SAM7S128 • AT91SAM7S256 • AT91SAM7S512 • AT91SAM7SE32 •...
Page 135 In order to work with an ATMEL AT91SAM7 device, it has to be initialized. The follow- ing paragraph describes the steps of an init sequence. An example for different soft- ware tools, such as J-Link GDB Server, IAR Workbench and RDI, is given. •...
Page 136: At91Sam9
J-Link. 7.2.2.1 JTAG settings We recommend using adaptive clocking. This information is applicable to the following devices: • AT91RM9200 • AT91SAM9260 • AT91SAM9261 • AT91SAM9262 • AT91SAM9263 J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 137: Freescale
Freescale J-Link has been tested with the following Freescale devices, but should work with any ARM7/9 and Cortex-M3 device: • MAC7101 • MAC7106 • MAC7111 • MAC7112 • MAC7116 • MAC7121 • MAC7122 • MAC7126 • MAC7131 • MAC7136 •...
Page 138: Luminary Micro
CHAPTER 7 Device specifics Luminary Micro J-Link has been tested with the following Luminary Micro devices, but should work with any ARM7/9 and Cortex-M3 device: • LM3S101 • LM3S102 • LM3S301 • LM3S310 • LM3S315 • LM3S316 • LM3S317 •...
Page 139: Stellaris Lm3S100 Series
7.4.1 Stellaris LM3S100 Series These device are Cortex-M3 based. All devices of this family are supported by J-Link. 7.4.2 Stellaris LM3S300 Series These device are Cortex-M3 based. All devices of this family are supported by J-Link. 7.4.3 Stellaris LM3S600 Series These device are Cortex-M3 based.
Page 140: Nxp
CHAPTER 7 Device specifics J-Link has been tested with the following NXP devices, but should work with any ARM7/9 and Cortex-M3 device: • LPC1111 • LPC1113 • LPC1311 • LPC1313 • LPC1342 • LPC1343 • LPC1751 • LPC1751 • LPC1752 •...
Page 141: Lpc
Indirectly reading solves the fast GPIO problem, because only direct regis- ter access corrupts the register contents. Define a 256 byte aligned area in RAM of the LPC target device with the J-Link com- mand map ram and define afterwards the memory area which should be read indirect with the command map indirectread to use the indirectly reading feature of J-Link.
Page 142 PC (R15) manually, after reset in order to debug the application. LPC288x flash programming In order to use the LPC288x devices in combination with J-Link FlashDL the applica- tion you are trying to debug, should be linked to the original flash @ addr 0x10400000.
Page 143: Oki
J-Link has been tested with the following OKI devices, but should work with any ARM7/9 and Cortex-M3 device: • ML67Q4002 • ML67Q4003 • ML67Q4050 • ML67Q4051 • ML67Q4060 • ML67Q4061 If you experience problems with a particular device, do not hesitate to contact Seg- ger.
Page 144: St Microelectronics
CHAPTER 7 Device specifics ST Microelectronics J-Link has been tested with the following ST Microelectronics devices, but should work with any ARM7/9 and Cortex-M3 device: • STR710FZ1 • STR710FZ2 • STR711FR0 • STR711FR1 • STR711FR2 • STR712FR0 • STR712FR1 •...
Page 145: Str 71X
All devices of this family are supported by J-Link. 7.7.4.1 Flash erasing The devices have 3 TAP controllers built-in. When starting J-Link.exe, it reports 3 JTAG devices. A special tool, J-Link STR9 Commander (JLinkSTR91x.exe) is available to directly access the flash controller of the device. This tool can be used to erase the flash of the controller even if a program is in flash which causes the ARM core to stall.
Page 146 Disabling the hardware watchdog In order to disable the hardware watchdog the option bytes have to be re-pro- grammed. SEGGER offers a free command line tool which reprograms the option bytes in order to disable the hardware watchdog. For more information about the STM32 commander, please refer to J-Link STM32 Commander (Command line tool) on page 60.
Page 147: Texas Instruments
Texas Instruments J-Link has been tested with the following Texas Instruments devices, but should work with any ARM7/9 and Cortex-M3 device: • TMS470R1A64 • TMS470R1A128 • TMS470R1A256 • TMS470R1A288 • TMS470R1A384 • TMS470R1B512 • TMS470R1B768 • TMS470R1B1M • TMS470R1VF288 •...
Page 149: Target Interfaces And Adapters
Chapter 8 Target interfaces and adapters This chapter gives an overview about J-Link / J-Trace specific hardware details, such as the pinouts and available adapters. J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 150: 20-Pin Jtag/Swd Connector
RESET pin of the target CPU, which is typically called "nRST", "nRESET" or "RESET". This pin is not connected in J-Link. It is reserved for com- patibility with other equipment to be used as a debug DBGRQ request signal to the target system. Typically connected to DBGRQ if available, otherwise left open.
Page 151 Pins 4, 6, 8, 10, 12, 14, 16, 18, 20 are GND pins connected to GND in J-Link. They should also be connected to GND in the target system. 8.1.1.1 Target board design We strongly advise following the recommendations given by the chip manufacturer.
Page 152: Pinout For Swd
Not con- This pin is not connected in J-Link. nected This pin is not used by J-Link. If the device may also be Not Used NC accessed via JTAG, this pin may be connected to nTRST, otherwise leave open.
Page 153 152. Table 8.3: J-Link / J-Trace SWD pinout Pins 4, 6, 8, 10, 12, 14, 16, 18, 20 are GND pins connected to GND in J-Link. They should also be connected to GND in the target system. J-Link / J-Trace (UM08001)
Page 154 Pin 19 of the connector can be used to supply power to the target hardware. Supply voltage is 5V, max. current is 300mA. The output current is monitored and protected against overload and short-circuit. Power can be controlled via the J-Link commander. The following commands are available to control power: Command...
Page 155: 38-Pin Mictor Jtag And Trace Connector
Target board Target board Target board Target board Target board Trace JTAG Trace JTAG Trace JTAG connector connector connector connector connector connector Target board Target board Target board J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 156: Pinout
Trace signal. For more information, please refer to Trace signal 10 Assignment of trace information pins between ETM archi- tecture versions on page 156. nTRST Active-low JTAG reset Table 8.5: JTAG+Trace connector pinout J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 157 Trace signal 16 Trace signal 4 Trace signal 15 Trace signal 3 Trace signal 14 Trace signal 2 Trace signal 13 Trace signal 1 Table 8.5: JTAG+Trace connector pinout J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 158: Assignment Of Trace Information Pins Between Etm Architecture Versions
TRACE- CLK. Parameter Min. Max. Explanation Tperiod 1000ns Clock period Fmax 1MHz 200MHz Maximum trace frequency 2.5ns High pulse width 2.5ns Low pulse width Table 8.7: Clock frequency J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 159 J-Trace supports half-rate clocking mode. Data is output on each edge of the TRACECLK signal and TRACECLK (max) <= 100MHz. For half-rate clocking, the setup and hold times at the JTAG+Trace connector must be observed. J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 160: 19-Pin Jtag/Swd And Trace Connector
TRACECLK 5V-Supply TRACEDATA[0] TRACEDATA[1] TRACEDATA[2] TRACEDATA[3] The following table lists the J-Link / J-Trace SWD pinout. SIGNAL TYPE Description This is the target reference voltage. It is used to check if the target has power, to create the logic-level reference...
Page 161: Target Power Supply
Pin 19 of the connector can be used to supply power to the target hardware. Supply voltage is 5V, max. current is 300mA. The output current is monitored and protected against overload and short-circuit. Power can be controlled via the J-Link commander. The following commands are available to control power: Command...
Page 162: Adapters
8.4.1 JTAG isolator J-Link JTAG Isolator can be connected between J-Link and any ARM target that uses the standard 20-pin JTAG-ARM connector to provide electrical isolation. This is essen- tial when the development tools are not connected to the same ground as the appli- cation.
Page 163: Jtag 14 Pin Adapter
Flat cable 8.4.2 JTAG 14 pin adapter An adapter is available to use J-Link / J-Trace with targets using this 14 pin 0.1" mat- ing JTAG connector. The following table shows the mapping between the 14 pin adapter and the standard 20 pin JTAG interface.
Page 164: Volt Adapter
JTAG probes) to 5V. Most targets have JTAG signals at voltage levels between 1.2V and 3.3V for J-Link and 3.0V up to 3.6V for J-Trace. These targets can be used with J-Link / J-Trace without a 5V adapter. Higher voltages are common primarily in the automotive sector.
Page 165 Adapter Target J-Link Flat cable Adapter Target J-Link Flat cable J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 166 CHAPTER 8 Target interfaces and adapters J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 167: Background Information
ARM9 architecture is based on Reduced Instruction Set Computer (RISC) principles. The instruction set and the related decode mechanism are greatly simplified com- pared with microprogrammed Complex Instruction Set Computer (CISC). J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 168: Jtag
The instruction register holds the current instruction and its content is used by the TAP controller to decide which test to perform or which data register to access. It consist of at least two shift-register cells. J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 169: The Tap Controller
Data may be loaded in parallel to the selected test data registers. Shift-DR The test data register connected between TDI and TDO shifts data one stage towards the serial output with each clock. J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 170 Once latched, this new instruction becomes the cur- rent one. The parallel latch prevents changes at the parallel output of the instruction register from occurring during the shifting process. J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 171: The Arm Core
Table 9.3: Registers of the ARM core = indicates that the normal register used by User or System mode has been replaced by an alternative register specific to the exception mode. J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 172: Arm / Thumb Instruction Set
Thumb mode can actually be as fast or faster than ARM mode. Mixing ARM and Thumb code (interworking) is possible. J-Link / J-Trace fully supports debugging of both modes without limitation. J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 173: Embeddedice
With software breakpoints, the instruction in memory is modi- fied. This does not work when debugging programs located in ROM or flash, but has one huge advantage: The number of software breakpoints is not limited. J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 174: The Ice Registers
Watchpoint 1 control mask Table 9.4: Function and mapping of EmbeddedICE registers For more information about EmbeddedICE, see the technical reference manual of your ARM CPU. ( www.arm.com ) J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 175: Embedded Trace Macrocell (Etm)
In the following a sample integration of J-Trace and the trace functionality on the debugger side is shown. The sample is based on IAR’s EWARM integration of J-Trace. J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 176 CHAPTER 9 Background information 9.4.3.1 Code coverage - Disassembly tracing J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 177 9.4.3.2 Code coverage - Source code tracing J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 179: Embedded Trace Buffer (Etb)
No additional special trace port is required, so that the ETB can be read via J-Link. The trace functionality via J-Link is limited by the size of the ETB. While capturing runs, the trace information in the buffer will be overwritten every time the buffer size has been reached.
Page 180: Flash Programming
Background information Flash programming J-Link / J-Trace comes with a DLL, which allows - amongst other functionalities - reading and writing RAM, CPU registers, starting and stopping the CPU, and setting breakpoints. The standard DLL does not have API functions for flash programming.
Page 181 RDI, (Remote debug interface) is a standard for "debug transfer agents" such as J- Link. It allows using J-Link from any RDI compliant debugger. RDI by itself does not include download to flash. To debug in flash, you need to somehow program your application program (debuggee) into the flash.
Page 182: J-Link / J-Trace Firmware
Every time you connect to J-Link / J-Trace, JLinkARM.dll checks if its embedded firm- ware is newer than the one used the J-Link / J-Trace. The DLL will then update the firmware automatically. This process takes less than 3 seconds and does not require a reboot.
Page 183 JLinkARM.dll. This automatically replaces the invalidated firmware with its embedded firmware. In the screenshot: • The red box identifies the new firmware. • The green box identifies the old firmware which has been replaced. J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 185: Designing The Target Board For Trace
Chapter 10 Designing the target board for trace This chapter describes the hardware requirements which have to be met by the tar- get board. J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 186: Overview Of High-Speed Board Design
The decision is related to track length between the ASIC and the JTAG+Trace connector, see Terminating the trace signal on page 185 for further ref- erence. J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 187: Terminating The Trace Signal
Care must be taken not to connect devices in this way, unless the distor- tion does not affect device operation. J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 188: Signal Requirements
Fmax 200MHz Ts setup time (min.) 2.0ns Th hold time (min.) 1.0ns TRACECLK high pulse width (min.) 1.5ns TRACECLK high pulse width (min.) 1.5ns Table 10.1: Signal requirements J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 189: Support And Faqs
Support and FAQs This chapter contains troubleshooting tips together with solutions for common prob- lems which might occur when using J-Link / J-Trace. There are several steps you can take before contacting support. Performing these steps can solve many problems and often eliminates the need for assistance.
Page 190: Measuring Download Speed
USB 2.0 port • USB 2.0 hub • J-Link • Target with ARM7 running at 50MHz. Below is a screenshot of JLink.exe after the measurement has been performed. J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 191: Troubleshooting
12. Start JLink.exe . 13. If JLink.exe displays the J-Link / J-Trace serial number and the target proces- sor’s core ID, the J-Link / J-Trace is working properly and cannot be the cause of your problem. 14. If JLink.exe is unable to read the target processor’s core ID you should analyze the communication between your target and J-Link / J-Trace with a logic analyzer or oscilloscope.
Page 192 CHAPTER 11 Support and FAQs J-Link/J-Trace does not get any connection to the target Most likely reasons: a.) The JTAG cable is defective. b.) The target hardware is defective. Remedy: Follow the steps described in section 11.2.1. J-Link / J-Trace (UM08001)
Page 193: Signal Analysis
J-Link / J-Trace and the target device. 11.3.1 Start sequence This is the signal sequence output by J-Link / J-Trace at start of JLink.exe . It should be used as reference when tracing potential J-Link / J-Trace related hardware prob- lems.
Page 194: Contacting Support
General procedure on page 189. You may also try your J-Link / J-Trace with another PC and if possible with another target system to see if it works there. If the device functions correctly, the USB setup on the original machine or your target hardware is the source of the problem, not J-Link / J-Trace.
Page 195: Frequently Asked Questions
Can J-Link / J-Trace read back the status of the JTAG pins? Yes, the status of all pins can be read. This includes the outputs of J-Link / J-Trace as well as the supply voltage, which can be useful to detect hardware problems on the target system.
Page 196 Registers on ARM 7 / ARM 9 targets I’m running J-Link.exe in parallel to my debugger, on an ARM 7 target. I can read memory okay, but the processor registers are different. Is this normal? If memory on an ARM 7/9 target is read or written the processor registers are modified.
Page 197: Glossary
Chapter 12 Glossary This chapter describes important terms used throughout this manual. J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 198 Glossary Adaptive clocking A technique in which a clock signal is sent out by J-Link / J-Trace. J-Link / J-Trace waits for the returned clock before generating the next clock pulse. The technique allows the J-Link / J-Trace interface unit to adapt to differing signal drive capabilities and differing cable lengths.
Page 199 Open collector A signal that may be actively driven LOW by one or more drivers, and is otherwise passively pulled HIGH. Also known as a "wired AND" signal. J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 200 The electronic clock signal which times data on the TAP data lines TMS, TDI, and TDO. The electronic signal input to a TAP controller from the data source (upstream). Usu- ally, this is seen connecting the J-Link / J-Trace Interface Unit to the first TAP control- ler. J-Link / J-Trace (UM08001)
Page 201 The electronic signal output from a TAP controller to the data sink (downstream). Usually, this is seen connecting the last TAP controller to the J-Link / J-Trace Inter- face Unit. Test Access Port (TAP) The port used to access a device's TAP Controller. Comprises TCK, TMS, TDI, TDO, and nTRST (optional).
Page 203 Chapter 13 Literature and references This chapter lists documents, which we think may be useful to gain deeper under- standing of technical details. J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 204 [RVI] Trace User Guide, ARM DUI ments on the target side. 0155C It is publicly available from ARM ( www.arm.com ). Table 13.1: Literature and References J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 205 Processor Core ........198 IEEE 1149.1 ........197 Program Status Register (PSR) ....198 Image ..........197 In-Circuit Emulator ......197 Instruction Register ......197 RDI Support ........64 IR ............ 197 J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...
Page 206 TCK .......... 148, 198 TDI .......... 148, 198 TDO ......... 148, 199 Test Access Port (TAP) ......199 Transistor-transistor logic (TTL) ... 199 Watchpoint ........ 171, 199 Word ..........199 J-Link / J-Trace (UM08001) © 2004-2009 SEGGER Microcontroller GmbH & Co. KG...

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J-trace

Segger J-Link User Manual

1 Introduction

2 Licensing

3 Setup

4 Link and J-Trace Related Software

5 Working with J-Link and J-Trace

6 Flash Download and Flash Breakpoints

7 Device Specifics

8 Target Interfaces and Adapters

9 Background Information

10 Designing the Target Board for Trace

11 Support and Faqs

12 Glossary

Quick Links

Troubleshooting

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