Reset Strategies; Strategies For Arm 7/9 Devices - Segger J-Link User Manual

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5.9

Reset strategies

J-Link / J-Trace supports different reset strategies. This is necessary because there is no
single way of resetting and halting a CPU core before it starts to execute instructions. For
example reset strategies which use the reset pin can not succeed on targets where the
reset pin of the CPU is not connected to the reset pin of the JTAG connector. Reset strategy
0 is always the recommended one because it has been adapted to work on every target
even if the reset pin (Pin 15) is not connected.
What is the problem if the core executes some instructions after RESET?
The instructions which are executed can cause various problems. Some cores can be com-
pletely "confused", which means they can not be switched into debug mode (CPU can not be
halted). In other cases, the CPU may already have initialized some hardware components,
causing unexpected interrupts or worse, the hardware may have been initialized with ille-
gal values. In some of these cases, such as illegal PLL settings, the CPU may be operated
beyond specification, possibly locking the CPU.
5.9.1

Strategies for ARM 7/9 devices

5.9.1.1 Type 0: Hardware, halt after reset (normal)
The hardware reset pin is used to reset the CPU. After reset release, J-Link continuously
tries to halt the CPU. This typically halts the CPU shortly after reset release; the CPU can
in most systems execute some instructions before it is halted. The number of instructions
executed depends primarily on the JTAG speed: the higher the JTAG speed, the faster the
CPU can be halted.
Some CPUs can actually be halted before executing any instruction, because the start of
the CPU is delayed after reset release. If a pause has been specified, J-Link waits for the
specified time before trying to halt the CPU. This can be useful if a bootloader which resides
in flash or ROM needs to be started after reset.
This reset strategy is typically used if nRESET and nTRST are coupled. If nRESET and nTRST
are coupled, either on the board or the CPU itself, reset clears the breakpoint, which means
that the CPU can not be stopped after reset with the BP@0 reset strategy.
5.9.1.2 Type 1: Hardware, halt with BP@0
The hardware reset pin is used to reset the CPU. Before doing so, the ICE breaker is pro-
grammed to halt program execution at address 0; effectively, a breakpoint is set at address
0. If this strategy works, the CPU is actually halted before executing a single instruction.
This reset strategy does not work on all systems for two reasons:
• If nRESET and nTRST are coupled, either on the board or the CPU itself, reset clears the
breakpoint, which means the CPU is not stopped after reset.
• Some MCUs contain a bootloader program (sometimes called kernel), which needs to
be executed to enable JTAG access.
5.9.1.3 Type 2: Software, for Analog Devices ADuC7xxx MCUs
This reset strategy is a software strategy. The CPU is halted and performs a sequence which
causes a peripheral reset. The following sequence is executed:
• The CPU is halted.
• A software reset sequence is downloaded to RAM.
• A breakpoint at address 0 is set.
• The software reset sequence is executed.
This sequence performs a reset of CPU and peripherals and halts the CPU before executing
instructions of the user program. It is the recommended reset sequence for Analog Devices
ADuC7xxx MCUs and works with these chips only.
J-Link / J-Trace (UM08001)
CHAPTER 5
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Reset strategies