J-Link Lite Arm - Segger J-Link User Manual

• Galvanic isolation from host via Ethernet
1.3.4.2 Hardware versions
Version 1.1
Compatible to J-Link.
• Provides an additional Ethernet interface which allows to communicate with J-
Link via TCP/IP.
Version 4
• New design based on STM32F407 + FPGA (Cyclone IV)Version 4.3
Identical to version 4 with the following exception:
• Pin 1 (VTref) is used for measuring target reference voltage only. Buffers on J-
Link side are no longer powered through this pin but via the J-Link internal volt-
age supplied via USB.
1.3.5

J-Link Lite ARM

J-Link Lite ARM is a fully functional OEM-version of J-Link. If
you are selling evaluation-boards, J-Link Lite ARM is an inex-
pensive emulator solution for you. Your customer receives a
widely acknowledged JTAG-emulator which allows him to start
right away with his development.
1.3.5.1 Additional features
• Very small form factor
• Fully software compatible to J-Link
• Supports any ARM7/9/11, Cortex-A5/A8/A9, Cortex-M0/M0+/M1/M3/M4, Cortex-
R4/R5 core
• JTAG clock up to 4 MHz
• SWD, SWO supported for Cortex-M devices
• Flash download into supported MCUs
• Standard 20-pin 0.1 inch JTAG connector (compatible to J-Link)
1.3.5.2 Specifications
The following table gives an overview about the specifications (general, mechanical,
electrical) for J-Link Lite ARM. All values are valid for J-Link hardware version 8.
Supported OS
Electromagnetic compatibility (EMC)
Operating temperature
Storage temperature
Relative humidity (non-condensing)
Size (without cables)
Weight (without cables)
USB interface
Target interface
Table 1.3: J-Link Lite specifications
J-Link / J-Trace (UM08001)
General
For a complete list of all operating sys-
tems which are supported, please refer
to Supported OS on page 23.
EN 55022, EN 55024
+5°C ... +60°C
-20°C ... +65 °C
Max. 90% rH
28mm x 26mm x 7mm
6g
Mechanical
USB 2.0, full speed
JTAG 20-pin
(14-pin adapter available)
JTAG/SWD Interface, Electrical
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