Strategies For Cortex-M Devices - Segger J-Link User Manual

5.8.2

Strategies for Cortex-M devices

J-Link supports different specific reset strategies for the Cortex-M cores. All of the
following reset strategies are available in JTAG and in SWD mode. All of them halt the
CPU after the reset.
Note: It is recommended that the correct device is selected in the debugger so
the debugger can pass the device name to the J-Link DLL which makes it possible for
J-Link to detect what is the best reset strategy for the device. Moreover, we recom-
mend that the debugger uses reset type 0 to allow J-Link to dynamically select what
reset is the best for the connected device.
5.8.2.1 Type 0: Normal
This is the default strategy. It does whatever is the best way to reset the target
device.
If the correct device is selected in the debugger this reset strategy may also perform
some special handling which might be necessary for the connected device. This for
example is the case for devices which have a ROM bootloader that needs to run after
reset and before the user application is started (especially if the debug interface is
disabled after reset and needs to be enabled by the ROM bootloader).
For most devices, this reset strategy does the same as reset strategy 8 does:
1. Make sure that the device halts immediately after reset (before it can execute any
instruction of the user application) by setting the VC_CORERESET in the DEMCR.
2. Reset the core and peripherals by setting the SYSRESETREQ bit in the AIRCR.
3. Wait for the S_RESET_ST bit in the DHCSR to first become high (reset active) and
then low (reset no longer active) afterwards.
4. Clear VC_CORERESET.
5.8.2.2 Type 1: Core
Only the core is reset via the VECTRESET bit. The peripherals are not affected. After
setting the VECTRESET bit, J-Link waits for the S_RESET_ST bit in the Debug Halting
Control and Status Register (DHCSR) to first become high and then low afterwards.
The CPU does not start execution of the program because J-Link sets the
VC_CORERESET bit before reset, which causes the CPU to halt before execution of the
first instruction.
Note: In most cases it is not recommended to reset the core only since most tar-
get applications rely of the reset state of some peripherals (PLL, External memory
interface etc.) and may be confused if they boot up but the peripherals are already
configured.
5.8.2.3 Type 2: ResetPin
J-Link pulls its RESET pin low to reset the core and the peripherals. This normally
causes the CPU RESET pin of the target device to go low as well, resulting in a reset
of both CPU and peripherals. This reset strategy will fail if the RESET pin of the target
device is not pulled low. The CPU does not start execution of the program because J-
Link sets the VC_CORERESET bit before reset, which causes the CPU to halt before
execution of the first instruction.
5.8.2.4 Type 3: Connect under Reset
J-Link connects to the target while keeping Reset active (reset is pulled low and
remains low while connecting to the target). This is the recommended reset strategy
for STM32 devices. This reset strategy has been designed for the case that communi-
cation with the core is not possible in normal mode so the VC_CORERESET bit can not
be set in order to guarantee that the core is halted immediately after reset.
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