Segger J-Trace for Cortex-M Debug Probe Manuals

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Segger J-Trace for Cortex-M User Manual

Segger J-Trace for Cortex-M User Manual (274 pages)

Brand: Segger | Category: Computer Accessories | Size: 2 MB

Table of Contents

Table of Contents
13
1 Introduction

19
- Requirements
  20
- Supported os
  21
- J-Link / J-Trace Models
  22
- Model Comparison
  23
- J-Link ARM
  24
- J-Link Ultra
  27
- J-Link ARM Pro
  28
- J-Link ARM Lite
  29
- J-Link Lite Cortex-M
  30
- J-Trace ARM
  32
- J-Trace for Cortex-M
  34
- Flasher ARM
  36
- J-Link Coldfire
  37
- Common Features of the J-Link Product Family
  38
- Supported CPU Cores
  39
- Built-In Intelligence for Supported CPU-Cores
  40
- Intelligence in the J-Link Firmware
  40
- Intelligence on the PC-Side (DLL)
  40
- Firmware Intelligence Per Model
  42
- Supported Ides
  44
2 Licensing

45
- Introduction
  46
- Software Components Requiring a License
  47
- License Types
  48
- Built-In License
  48
- Key-Based License
  48
- Device-Based License
  49
- Legal Use of SEGGER J-Link Software
  52
- Use of the Software with 3Rd Party Tools
  52
- Original SEGGER Products
  53
- J-Link
  53
- J-Link Ultra
  53
- J-Link Pro
  54
- J-Trace
  54
- J-Trace for Cortex-M
  55
- Flasher ARM
  55
- J-Link OEM Versions
  56
- Analog Devices: Midaslink
  56
- Atmel: SAM-ICE
  56
- Digi: JTAG Link
  57
- IAR: J-Link / J-Link KS
  57
- IAR: J-Link Lite
  57
- IAR: J-Trace
  58
- NXP: J-Link Lite LPC Edition
  58
- SEGGER: J-Link Lite
  58
- J-Link Obs
  59
- Illegal Clones
  60
3 Link and J-Trace Related Software

61
4 Setup

79
5 Working with J-Link and J-Trace

93
- Connecting the Target System
  94
- Power-On Sequence
  94
- Verifying Target Device Connection
  94
- Problems
  94
- Indicators
  95
- Main Indicator
  95
- Input Indicator
  97
- Output Indicator
  97
- JTAG Interface
  98
- Multiple Devices in the Scan Chain
  98
- Sample Configuration Dialog Boxes
  98
- Determining Values for Scan Chain Configuration
  101
- JTAG Speed
  102
- SWD Interface
  103
- SWD Speed
  103
- Swo
  103
- Multi-Core Debugging
  105
- How Multi-Core Debugging Works
  105
- Using Multi-Core Debugging in Detail
  106
- Things You Should be Aware of
  107
- Connecting Multiple J-Links / J-Traces to Your PC
  109
- How Does It Work
  109
- J-Link Control Panel
  111
- Tabs
  111
- Reset Strategies
  117
- Strategies for ARM 7/9 Devices
  117
- Strategies for Cortex-M Devices
  119
- Using DCC for Memory Access
  121
- What Is Required
  121
- Target DCC Handler
  121
- Target DCC Abort Handler
  121
- J-Link Script Files
  122
- Actions that Can be Customized
  122
- Script File API Functions
  122
- Global DLL Variables
  126
- Global DLL Constants
  129
- Script File Language
  130
- Script File Writing Example
  131
- Executing J-Link Script Files
  131
- Command Strings
  133
- List of Available Commands
  133
- Using Command Strings
  139
- Switching off CPU Clock During Debug
  141
- Cache Handling
  142
- Cache Coherency
  142
- Cache Clean Area
  142
- Cache Handling of ARM7 Cores
  142
- Cache Handling of ARM9 Cores
  142
6 Flash Download

143
- Introduction
  144
- Licensing
  145
- Supported Devices
  146
- Setup for Various Debuggers (Internal Flash)
  147
- IAR Embedded Workbench
  147
- Keil MDK
  147
- J-Link GDB Server
  149
- J-Link Commander
  150
- J-Link RDI
  150
- Setup for Various Debuggers (CFI Flash)
  151
- IAR Embedded Workbench / Keil MDK
  151
- J-Link GDB Server
  152
- J-Link Commander
  152
- Using the DLL Flash Loaders in Custom Applications
  153
7 Flash Breakpoints

155
- Introduction
  156
- Licensing
  157
- 24H Flash Breakpoint Trial License
  157
- Supported Devices
  158
- Setup & Compatibility with Various Debuggers
  159
- Setup
  159
- Compatibility with Various Debuggers
  159
- Faq
  160
8 Rdi

161
- Introduction
  162
- Features
  162
- Licensing
  163
- Setup for Various Debuggers
  164
- IAR Embedded Workbench IDE
  164
- ARM AXD (ARM Developer Suite, ADS)
  167
- ARM RVDS (Realview Developer Suite)
  169
- Ghs Multi
  174
- KEIL MDK (Μvision IDE)
  177
- Configuration
  180
- Configuration File Jlinkrdi.ini
  180
- Using Different Configurations
  180
- Using Mutliple J-Links Simulatenously
  180
- Configuration Dialog
  180
- Semihosting
  189
- Overview
  189
- The SWI Interface
  189
- Implementation of Semihosting in J-Link RDI
  190
- Semihosting with AXD
  190
- Unexpected / Unhandled Swis
  191
9 Device Specifics

193
- Analog Devices
  194
- Aduc7Xxx
  194
- Atmel
  196
- At91Sam7
  197
- At91Sam9
  199
- Dspgroup
  200
- Ember
  201
- Energy Micro
  202
- Freescale
  203
- Kinetis Family
  203
- Unlocking
  203
- Tracing
  204
- Fujitsu
  205
- Itron
  206
- Luminary Micro
  207
- Unlocking Lm3Sxxx Devices
  208
- Nxp
  209
- LPC ARM7-Based Devices
  210
- Reset (Cortex-M3 Based Devices)
  211
- Lpc288X Flash Programming
  211
- Lpc43Xx
  211
- Oki
  212
- Renesas
  213
- Samsung
  214
- S3Fn60D
  214
- ST Microelectronics
  215
- Str91X
  216
- Stm32F10Xxx
  216
- Stm32F2Xxx
  218
- Stm32F4Xxx
  218
- Texas Instruments
  220
- Am335X
  220
- Am35Xx / Am37Xx
  221
- Omap4430
  221
- Omap-L138
  221
- Tms470M
  221
- Omap3530
  222
- Omap3550
  222
- Toshiba
  223
10 Target Interfaces and Adapters

225
- 20-Pin JTAG/SWD Connector
  226
- Pinout for JTAG
  226
- Pinout for SWD
  229
- 38-Pin Mictor JTAG and Trace Connector
  231
- Connecting the Target Board
  231
- Pinout
  232
- Assignment of Trace Information Pins between ETM Architecture Versions
  234
- Trace Signals
  234
- 19-Pin JTAG/SWD and Trace Connector
  236
- Target Power Supply
  237
- 9-Pin JTAG/SWD Connector
  238
- Adapters
  239
11 Background Information

241
- Jtag
  242
- Test Access Port (TAP)
  242
- Data Registers
  242
- Instruction Register
  242
- The TAP Controller
  243
- Embedded Trace Macrocell (ETM)
  245
- Trigger Condition
  245
- Code Tracing and Data Tracing
  245
- J-Trace Integration Example - IAR Embedded Workbench for ARM
  245
- Embedded Trace Buffer (ETB)
  249
- Flash Programming
  250
- How Does Flash Programming Via J-Link / J-Trace Work
  250
- Data Download to RAM
  250
- Data Download Via DCC
  250
- Available Options for Flash Programming
  250
- J-Link / J-Trace Firmware
  252
- Firmware Update
  252
- Invalidating the Firmware
  252
12 Designing the Target Board for Trace

255
- Overview of High-Speed Board Design
  256
- Avoiding Stubs
  256
- Minimizing Signal Skew (Balancing PCB Track Lengths)
  256
- Minimizing Crosstalk
  256
- Using Impedance Matching and Termination
  256
- Terminating the Trace Signal
  257
- Rules for Series Terminators
  257
- Signal Requirements
  258
13 Support and Faqs

259
- Measuring Download Speed
  260
- Test Environment
  260
- Troubleshooting
  261
- General Procedure
  261
- Typical Problem Scenarios
  261
- Contacting Support
  263
- Frequently Asked Questions
  264
14 Glossary

265

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