Strategies For Cortex-M3 Devices - Segger J-Link User Manual

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5.8.2

Strategies for Cortex-M3 devices

J-Link supports different specific reset strategies for the Cortex-M3 core. All of the
following reset strategies are available in JTAG and in SWD mode. All three reset
strategies halt the CPU after the reset.
5.8.2.1 Type 0: Normal
This reset strategy is the default strategy and should usually be used to reset the
target. When using this strategy, J-Link sets the VC_CORERESET bit before reset,
which causes the CPU to halt before execution of the first instruction. In addition to
that the SYSRESETREQ bit and the VECTRESET bit are also set in order to guarantee
that the core and the peripherals are reset even on targets where the CPU RESET pin
is not connected to Pin 15 (RESET) of the JTAG/SWD connector.
5.8.2.2 Type 1: Core
Only the core is reset via the VECTRESET bit. The peripherals are not affected. After
setting the VECTRESET bit, J-Link waits for the S_RESET_ST bit in the Debug Halting
Control and Status Register (DHCSR) to first become high and then low afterwards.
The CPU does not start execution of the program because J-Link sets the
VC_CORERESET bit before reset, which causes the CPU to halt before execution of
the first instruction.
5.8.2.3 Type 2: ResetPin
J-Link pulls its RESET pin low to reset the core and the peripherals. This normally
causes the CPU RESET pin of the target device to go low as well, resulting in a reset
of both CPU and peripherals. This reset strategy will fail if the RESET pin of the target
device is not pulled low. The CPU does not start execution of the program because J-
Link sets the VC_CORERESET bit before reset, which causes the CPU to halt before
execution of the first instruction.
J-Link / J-Trace (UM08001)
CHAPTER 5
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