Common Features Of The J-Link Product Family - Segger J-Link User Manual

Jtag emulators for arm cores
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Common features of the J-Link product family

USB 2.0 interface
Any ARM7/9/11 (including thumb mode), Cortex-M0/M1/M3 core supported
Automatic core recognition
Maximum JTAG speed 12 MHz
Seamless integration into the IAR Embedded Workbench® IDE
No power supply required, powered through USB
Support for adaptive clocking
All JTAG signals can be monitored, target voltage can be measured
Support for multiple devices
Fully plug and play compatible
Standard 20-pin JTAG connector, standard 38-pin JTAG+Trace connector
USB and 20-pin ribbon cable included
Memory viewer (J-Mem) included
TCP/IP server included, which allows using J-Trace via TCP/IP networks
RDI interface available, which allows using J-Link with RDI compliant software
Flash programming software (J-Flash) available
Flash DLL available, which allows using flash functionality in custom applications
Software Developer Kit (SDK) available
Full integration with the IAR C-SPY® debugger; advanced debugging features
available from IAR C-SPY debugger.
14-pin JTAG adapter available
Adapter for 5V JTAG targets available
Optical isolation adapter for JTAG/SWD interface available
Target power supply via pin 19 of the JTAG/SWD interface (up to 300 mA to tar-
get with overload protection)
J-Link / J-Trace (UM08001)
© 2004-2009 SEGGER Microcontroller GmbH & Co. KG
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