Page 1 J-Link / J-Trace User guide of the JTAG emulators for ARM Cores Software Version V4.26 Manual Rev. 0 Date: May 13, 2011 Document: UM08001 A product of SEGGER Microcontroller GmbH & Co. KG www.segger.com...
Page 2 Please make sure your manual is the latest edition. While the information herein is assumed to be accurate, SEGGER Microcontroller GmbH & Co. KG (the manufacturer) assumes no responsibility for any errors or omissions. The manufacturer makes and you receive no warranties or conditions, express, implied, statutory or in any communication with you.
Page 3 Chapter "J-Link and J-Trace related software" 100622 * Section "SWO Analyzer" added. 100617 Several corrections. Chapter "Introduction" * Section "J-Link / J-Trace models" updated. 100504 Chapter "Target interfaces and adapters" * Section "Adapters" updated. Chapter "Introduction" 100428 * Section "J-Link / J-Trace models" updated.
Page 4 * Section "J-Link / J-Trace models" updated. Chapter "Introduction" * Section" Specifications" updated * Section "Hardware versions" updated 090828 * Section "Common features of the J-Link product family" updated Chapter "Target interfaces and adapters" * Section "5 Volt adapter" updated Chapter "Introduction"...
Page 5 090108 updated. * Section "Target board design for SWD" added. Chapter "Working with J-Link Pro" 090105 * Section "Connecting J-Link Pro the first time" updated. Chapter "Working with J-Link Pro" * Section "Introduction" updated. * Section "Configuring J-Link Pro 081222 via web interface"...
Page 6 Revision Date Explanation Chapter "Licensing" added. Chapter "Hardware" 080904 Section "J-Link OEM versions" moved to chapter "Licensing" Chapter "Hardware" Section "JTAG+Trace connector" JTAG+Trace 080902 connector pinout corrected. Section "J-Link OEM versions" updated. Chapter "J-Link control panel" moved to chapter 080827 "Working with J-Link".
Page 7 Chapter "Hardware": 070320 "Using the JTAG connector with SWD" updated. Chapter "Hardware": 070316 "Using the JTAG connector with SWD" added. Chapter "Hardware": 070312 "Differences between different versions" supplemented. J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 8 Revision Date Explanation Chapter "J-Link / J-Trace related software": 070307 "J-Link GDB Server" licensing updated. Chapter "J-Link / J-Trace related software" updated and reorganized. 070226 Chapter "Hardware" "List of OEM products" updated Chapter "Device specifics" added 070221 Subchapter "Command strings" added Chapter "Hardware":...
Page 9 Revision Date Explanation 051021 Performance values updated. 051011 Chapter "Working with J-Link" added. 050818 Initial version. J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 11 For simplicity, we will refer to J-Link ARM as J-Link in this manual. For simplicity, we will refer to J-Link ARM Pro as J-Link Pro in this manual. Typographic conventions This manual uses the following typographic conventions:...
Page 12 Apart from its main focus on software tools, SEGGER develops and produces programming tools for flash microcontrollers, as well as J-Link, a JTAG emulator to assist in develop- ment, debugging and production, which has rapidly become the industry standard for debug access to ARM cores.
Page 13: Table Of Contents
J-Trace for Cortex-M ................34 1.3.9 Flasher ARM.................... 36 1.3.10 J-Link ColdFire ..................37 Common features of the J-Link product family ..........38 Supported CPU cores ................39 Built-in intelligence for supported CPU-cores ..........40 1.6.1 Intelligence in the J-Link firmware ............. 40 1.6.2...
Page 14 Installing the J-Link ARM software and documentation pack ......64 3.1.1 Setup procedure ..................64 Setting up the USB interface..............67 3.2.1 Verifying correct driver installation ............67 Uninstalling the J-Link USB driver .............. 69 Setting up the IP interface................ 70 3.4.1...
Page 15 5.6.1 How does it work? ................. 111 5.6.2 Configuring multiple J-Links / J-Traces ............. 112 5.6.3 Connecting to a J-Link / J-Trace with non default USB-Address ....113 J-Link control panel................114 5.7.1 Tabs ....................114 Reset strategies ..................120 5.8.1...
Page 16 9.2.3 J-Trace integration example - IAR Embedded Workbench for ARM....193 Embedded Trace Buffer (ETB) ..............197 Flash programming ................198 9.4.1 How does flash programming via J-Link / J-Trace work? ......198 9.4.2 Data download to RAM ................198 9.4.3 Data download via DCC................198 9.4.4...
Page 17 Signal analysis ..................211 11.3.1 Start sequence ..................211 11.3.2 Troubleshooting ..................211 11.4 Contacting support ................212 11.5 Frequently Asked Questions ..............213 12 Glossary........................215 13 Literature and references...................221 J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 19: Introduction
Chapter 1 Introduction This chapter gives a short overview about J-Link and J-Trace. J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 20: Requirements
Introduction Requirements Host System To use J-Link or J-Trace you need a host system running Windows 2000 or later. For a list of all operating systems which are supported by J-Link, please refer to Supported OS on page 21. Target System A target system with a supported CPU is required.
Page 21: Supported Os
Supported OS J-Link/J-Trace can be used on the following operating systems: • Microsoft Windows 2000 • Microsoft Windows XP • Microsoft Windows XP x64 • Microsoft Windows 2003 • Microsoft Windows 2003 x64 • Microsoft Windows Vista • Microsoft Windows Vista x64 •...
Page 22: J-Link / J-Trace Models
J-Links / J-Traces have the hardware version printed on the back label. If this is not the case with your J-Link / J-Trace, start JLink.exe. As part of the initial message, the hardware version is displayed.
Page 23: Model Comparison
JTAG ETM Trace Software features Software features are features implemented in the software primarily on the host. Software features can either come with the J-Link or be added later using a license string from Segger. J-Trace J-Link J-Link Pro...
Page 24: J-Link Arm
** = Measured with J-Link Rev.5, ARM7 @ 50 MHz, 12MHz JTAG speed. 1.3.2.2 Specifications The following table gives an overview about the specifications (general, mechanical, electrical) for J-Link ARM. All values are valid for J-Link ARM hardware version 8. General For a complete list of all operating sys- Supported OS tems which are supported, please refer to Supported OS on page 21.
Page 25 48 MHz / n, where n is 4, 5, ..., resulting in speeds of: 12.000 MHz (n = 4) 9.600 MHz (n = 5) 8.000 MHz (n = 6) 6.857 MHz (n = 7) 6.000 MHz (n = 8) J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 26 5V target supply (pin 19) of Kick-Start versions of J-Link is current monitored and limited. J-Link automatically switches off 5V supply in case of over-current to protect both J-Link and host computer. Peak current (<= 10 ms) limit is 1A, operating current limit is 300mA.
Page 27: J-Link Ultra
SPI 1.3.3.2 Specifications The following table gives an overview about the specifications (general, mechanical, electrical) for J-Link Ultra. All values are valid for J-Link Ultra hardware version 1. Note: Some specifications, especially speed, are likely to be improved in the future with newer versions of the J-Link software (freely available).
Page 28: J-Link Arm Pro
Table 1.3: J-Link Ultra specifications 1.3.4 J-Link ARM Pro J-Link Pro is a JTAG emulator designed for ARM cores. It is fully compatible to J-Link and connects via Ethernet/USB to a PC running Microsoft Windows 2000 or later. For a complete list of all operating systems which are supported, please refer to Sup- ported OS on page 19.
Page 29: J-Link Arm Lite
• RDI interface available, which allows using J-Link with RDI compliant software ** = Measured with J-Link Pro Rev. 1.1, ARM7 @ 50 MHz, 12MHz JTAG speed. 1.3.4.2 Download speed The following table lists performance values (Kbytes/s) for writing to memory (RAM):...
Page 30: J-Link Lite Cortex-M
Introduction 1.3.5.2 Specifications The following table gives an overview about the specifications (general, mechanical, electrical) for J-Link ARM Lite. All values are valid for J-Link ARM hardware version 8. General For a complete list of all operating sys- Supported OS tems which are supported, please refer to Supported OS on page 21.
Page 31 Data output rise time (T Max. 10ns Data output fall time (T Max. 10ns Clock rise time (T Max. 10ns Clock fall time (T Max. 10ns Table 1.6: J-Link Lite Cortex-M specifications J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 32: J-Trace Arm
Target Interface JTAG+Trace: Mictor, 38-pin JTAG/SWD Interface, Electrical Power Supply USB powered < 300mA Supported Target interface voltage 3.0 - 3.6 V (5V adapter available) Table 1.7: J-Trace specifications J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 33 The actual speed depends on various factors, such as JTAG, clock speed, host CPU core etc. 1.3.7.4 Hardware versions Version 1 This J-Trace uses a 32-bit RISC CPU. Maximum download speed is approximately 420 KBytes/second (600 KBytes/second using DCC). J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 34: J-Trace For Cortex-M
J-Trace for Cortex-M is a JTAG/SWD emulator designed for Cor- tex-M cores which includes trace (ETM) support. J-Trace for Cortex-M can also be used as a J-Link and it also supports ARM7/9 cores. Tracing on ARM7/9 targets is not supported.
Page 35 Version 3.1 Identical to version 2.0 with the following exceptions: • Hi-Speed USB • Voltage range for trace signals extended to 1.2 - 3.3 V • Higher download speed J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 36: Flasher Arm
J-Flash soft- ware or stand-alone. In addition to that Flasher ARM has all of the J-Link functionality. For more information about Flasher ARM, please refer to UM08007, Flasher ARM User’s Guide. 1.3.9.1 Specifications The following table gives an overview about the specifications (general, mechanical, electrical) for Flasher ARM.
Page 37: J-Link Coldfire
10 kOhm Table 1.11: Flasher ARM specifications 1.3.10 J-Link ColdFire J-Link ColdFire is a BDM emulator designed for ColdFire® cores. It connects via USB to a PC running Microsoft Windows 2000, Windows XP, Windows 2003, or Windows Vista. J-Link ColdFire has a built-in 26-pin BDM connector, which is compatible to the standard 26-pin connector defined by Freescale.
Page 38: Common Features Of The J-Link Product Family
Memory viewer (J-Mem) included • TCP/IP server included, which allows using J-Trace via TCP/IP networks • RDI interface available, which allows using J-Link with RDI compliant software • Flash programming software (J-Flash) available • Flash DLL available, which allows using flash functionality in custom applications •...
Page 39: Supported Cpu Cores
Supported CPU cores J-Link / J-Trace has been tested with the following cores, but should work with any ARM7/9/11, Cortex-M0/M1/M3/M4 and Cortex-A5/A8/R4 core. If you experience problems with a particular core, do not hesitate to contact Segger. • ARM7TDMI (Rev 1) •...
Page 40: Built-In Intelligence For Supported Cpu-Cores
CPU-core. If Intelligence in the firmware is available, it is used. If you are using a J-Link that does not have intelligence in the firmware and only PC-side intelligence is available for the connected CPU, a warning message is shown.
Page 41 (slow mode) will be more reliable but very slow due to the high number of USB/Ethernet transactions. It simply boils down to: The best solution is having intelligence in the emulator itself! J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 42 Instability, especially on slow targets Due to the fact that a lot of USB transactions would cause a very bad perfor- mance of J-Link, on PC-side implementations the assumption is made that the CPU/Debug interface is fast enough to handle the commands/requests without the need of waiting.
Page 43: Firmware Intelligence Per Model
1.6.3 Firmware intelligence per model There are different models of J-Link / J-Trace which have built-in intelligence for dif- ferent CPU-cores. In the following, we will give you an overview about which model of J-Link / J-Trace has intelligence for which CPU-core.
Page 44 CHAPTER 1 Introduction 1.6.3.2 Older models The table below lists the firmware CPU support for older J-Link & J-Trace models which are not sold anymore. Cortex- Renesas Cortex-M J-Link / J-Trace RX600 model JTAG JTAG JTAG JTAG JTAG not sup- J-Link "...
Page 45: Supported Ides
J-Link / J-Trace can be used with different IDEs. Some IDEs support J-Link directly, for other ones additional software (such as J-Link RDI) is necessary in order to use J- Link. The following tables list which features of J-Link / J-Trace can be used with the different IDEs.
Page 47: Licensing
Chapter 2 Licensing This chapter describes the different license types of J-Link related software and the legal use of the J-Link software with original SEGGER and OEM products. J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 48: Introduction
Licensing Introduction J-Link functionality can be enhanced by the features J-Flash, RDI, flash download and flash breakpoints (FlashBP). The flash breakpoint feature does not come with J-Link and need an additional license. In the following the licensing options of the software will be explained.
Page 49: Software Components Requiring A License
J-Link RDI • Flash breakpoints (FlashBP) For more information about J-Link RDI licensing procedure / license types, please refer to the J-Link RDI User Guide (UM08004), chapter Licensing. For more information about J-Flash licensing procedure / license types, please refer to the J-Flash User Guide (UM08003), chapter Licensing.
Page 50: License Types
Key-based license This type of license is used if you already have a J-Link, but want to enhance its func- tionality by using flash breakpoints. In addition to that, the key-based license is used for trial licenses.
Page 51: Device-Based License
The device-based license is a free license, available for some devices. It’s already included in J-Link, so no keys are necessary to enable this license type. To activate a device based license, the debugger needs to select a supported device.
Page 52 RDI, J-Link ARM FlashDL, J- LPC2378 Link ARM FlashBP RDI, J-Link ARM FlashDL, J- LPC2468 Link ARM FlashBP RDI, J-Link ARM FlashDL, J- LPC2478 Link ARM FlashBP Table 2.1: Device list J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 53: Legal Use Of Segger J-Link Software
Use of software SEGGER J-Link software may only be used with original SEGGER products and autho- rized OEM products. The use of the licensed software to operate SEGGER product clones is prohibited and illegal.
Page 54: Original Segger Products
CHAPTER 2 Licensing Original SEGGER products The following products are original SEGGER products for which the use of the J-Link software is allowed: 2.5.1 J-Link J-Link is a JTAG emulator designed for ARM cores. It connects via USB to a PC running Microsoft Windows 2000, Windows XP, Windows 2003, Windows Vista or Windows 7.
Page 55: J-Link Pro
2.5.3 J-Link Pro J-Link Pro is a JTAG emulator designed for ARM cores. It con- nects via USB or Ethernet to a PC running Microsoft Windows 2000, Windows XP, Windows 2003, Windows Vista or Windows 7. J-Link has a built-in 20-pin JTAG connector, which is compat- ible with the standard 20-pin connector defined by ARM.
Page 56: J-Trace For Cortex-M
J-Trace for Cortex-M is a JTAG/SWD emulator designed for Cor- tex-M cores which include trace (ETM) support. J-Trace for Cor- tex-M can also be used as a regular J-Link and it also supports ARM7/9 cores. Please note that tracing on ARM7/9 targets is not supported by J-Trace for Cortex-M.
Page 57: J-Link Oem Versions
In any case, it should be possible to use the J-Link software with these OEM versions. How- ever, proper function cannot be guaranteed for OEM versions. SEGGER Microcontrol- ler does not support OEM versions;...
Page 58: Digi: Jtag Link
Limitations Digi JTAG Link works with Digi devices only. This limitation can NOT be lifted; if you would like to use J-Link with a device from an other manufacturer, you need to buy a separate J-Link. Licenses License for GDB Server is included. Other licenses can be added.
Page 59: Iar: J-Trace
No licenses are included. All licenses can be added. Note J-Link ARM Lite is only delivered and supported as part of Starter Kits. It is not sold to end customer and not guaranteed to work with custom hardware. J-Link / J-Trace (UM08001)
Page 60: J-Link Obs
Licensing J-Link OBs J-Link OBs (J-Link On Board) are single chip versions of J-Link which are used on var- ious evalboards. It is legal to use J-Link software with these boards, provided that the eval board manufacturer has obtained a license from SEGGER. The following list shows the eval board manufacturer which are allowed to use J-Link OBs: •...
Page 61: Illegal Clones
The use of illegal J-Link clones with this software is a violation of US, European and other international laws and is prohibited. If you are in doubt if your unit may be legally used with SEGGER J-Link software, please get in touch with us.
Page 63: Setup
Chapter 3 Setup This chapter describes the setup procedure required in order to work with J-Link / J- Trace. Primarily this includes the installation of the J-Link software and documenta- tion package, which also includes a kernel mode J-Link USB driver in your host sys- tem.
Page 64: Installing The J-Link Arm Software And Documentation Pack
J-Link USB driver. Some of the applications require an additional license, free trial licenses are available upon request from www.segger.com. Refer to chapter J-Link and J-Trace related software on page 77 for an overview about the J-Link software and documentation pack. 3.1.1...
Page 65 The Choose options dialog is opened. The Create entry in start menu and the Add shortcuts to desktop option are preselected. Accept or deselect the options and confirm the selection with the Next > button. J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 66 The J-Link software and documentation pack is successfully installed on your PC. Connect your J-Link via USB with your PC. The J-Link will be identified and after a short period the J-Link LED stops rapidly flashing and stays on permanently.
Page 67: Setting Up The Usb Interface
In addition you can verify the driver installation by consulting the Windows device manager. If the driver is installed and your J-Link / J-Trace is connected to your com- puter, the device manager should list the J-Link USB driver as a node below "Univer- sal Serial Bus controllers"...
Page 68 Setup Right-click on the driver to open a context menu which contains the command Prop- erties. If you select this command, a J-Link driver Properties dialog box is opened and should report: This device is working properly. If you experience problems, refer to the chapter Support and FAQs on page 207 for help.
Page 69: Uninstalling The J-Link Usb Driver
Uninstalling the J-Link USB driver If J-Link / J-Trace is not properly recognized by Windows and therefore does not enu- merate, it makes sense to uninstall the J-Link USB driver. This might be the case when: • The LED on the J-Link / J-Trace is rapidly flashing.
Page 70: Setting Up The Ip Interface
Connecting J-Link only via Ethernet and read out the IP via the DHCP IP Assign- ment table of your DHCP Server. In the following, both ways to get the IP address assigned to J-Link via DHCP, are explained. 3.4.1.1 Connecting via USB and Ethernet When using JLink.exe in order to read out the IP address, J-Link has to be con-...
Page 71: Configuring The J-Link
By default, J-Link is configured to receive an IP address and a subnet mask via DHCP. It is also possible to assign a fixed IP address to it. Setting up J-Link can be done via JLink.exe or via web interface. In the following, both configuration methods are described.
Page 72 Setup Assigning an IP address manually If you do not want J-Link to be configured via DHCP, you can assign an IP address and a subnet mask (optional) manually. This is done via the ipaddr command in JLink.exe. This command can be used in four different ways, which are explained in...
Page 73: Faqs
3.4.3 FAQs How can I use J-Link with GDB and Ethernet? You have to use the J-Link ARM GDB Server in order to connect to J-Link via GDB and Ethernet. J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 74: J-Link Configurator
Setup J-Link configurator In general, there are two interfaces which can be used by J-Link, to connect to a host: USB Full/Hi-Speed and Ethernet. When using USB, there are different ways in which a J-Link can be identified on a host. The J-Link software and documentation package comes with a configurator (JLinkConfig.exe) which allows you to configure...
Page 75: Using The J-Link Configurator
3.5.2 Using the J-Link configurator When starting the J-Link configurator a dialog pops up which shows a list of all emu- lators which are currently connected to the PC by USB. The list is automatically upadted, so if you start the configurator first an then connect your J-Link to your PC, the configurator will recognize this and updates the list of emulators.
Page 76: Connecting To Different J-Links Via Usb
J-Links. If more than one J-Link has been found, a emulator selection dialog is shown, which enables you to select the correct one. So even in IDEs which do not have an selection option for the J-Link, it is possible to connect to different J-Links.
Page 77: Link And J-Trace Related Software
This chapter describes Segger’s J-Link / J-Trace related software portfolio, which cov- ers nearly all phases of the development of embedded applications. The support of the remote debug interface (RDI) and the J-Link GDBServer allows an easy J-Link integration in all relevant toolchains.
Page 78: J-Link Related Software
J-Link and J-Trace related software J-Link related software 4.1.1 J-Link software and documentation package J-Link is shipped with a bundle of applications. Some of the applications require an additional license, free trial licenses are available upon request from www.seg- ger.com. Software Description JLinkARM.dll...
Page 79: List Of Additional Software Packages
Command line tool that opens an svf file and sends the data in JTAGLoad it via J-Link / J-Trace to the target. J-Link Software The J-Link Software Developer Kit is needed if you want to Developer Kit write your own program with J-Link / J-Trace. (SDK) J-Link Flash Soft- An enhanced version of the JLinkARM.DLL, which contains...
Page 80: J-Link Software And Documentation Package In Detail
ARM core and the ICE breaker module. 4.2.1.1 Using command script files J-Link commander can also be used in script mode which allows the user to use J- Link commander for batch processing and without user interaction. When using J- Link commander in script mode, the path to a script file is passed to it.
Page 81: Swo Analyzer
Usage SWOAnalyzer.exe <SWOfile> This can be achieved by simply dragging the SWO output file created by the J-Link DLL onto the executable. Creating an SWO output file In order to create the SWO output file, which is th input file for the SWO Analyzer, the J-Link config file needs to be modified.
Page 82 GPIOs in output. The IOs are maintained in this state until a next JTAG instruction is send." (ST Microelectronics) Enabling Turbo Mode is necessary to guarantee proper function of all commands in the STR91x Commander. J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 83: J-Link Stm32 Commander (Command Line Tool)
4.2.4 J-Link STM32 Commander (Command line tool) J-Link STM32 Commander (JLinkSTM32.exe) is a free command line tool which can be used to disable the hardware watchdog of STM32 devices which can be activated by programming the option bytes. Moreover the J-Link STM32 Commander unsecures a read-protected STM32 device by re-programming the option bytes.
Page 84: J-Link Tcp/Ip Server (Remote J-Link / J-Trace Use)
The J-Link TCP/IP Server allows using J-Link / J-Trace remotely via TCP/IP. This enables you to connect to and fully use a J-Link / J-Trace from another computer. Performance is just slightly (about 10%) lower than with direct USB connection.
Page 85: J-Mem Memory Viewer
SFRs can be written. You can choose between 8/16/32-bit size for read and write accesses. J-Mem works nicely when modifying SFRs, especially because it writes the SFR only after the complete value has been entered. J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 86: J-Flash Arm (Program Flash Memory Via Jtag)
However, to actually program devices via J-Flash ARM and J-Link / J-Trace you are required to obtain a license key from us. Evaluation licenses are available free of charge. For further information go to our website or contact us directly.
Page 87: J-Link Rdi (Remote Debug Interface)
The J-Link RDI software is an remote debug interface for J-Link. It makes it possible to use J-Link with any RDI compliant debugger. The main part of the software is an RDI-compliant DLL, which needs to be selected in the debugger. There are two addi- tional features available which build on the RDI software foundation.
Page 88: J-Link Gdb Server
GDB is freely available from the GNU committee under: http://www.gnu.org/software/gdb/download/ J-Link GDB Server is distributed as "free for evaluation and non commercial use". The software can be used free of charge for educational and nonprofit purposes without additional license.
Page 89: Dedicated Flash Programming Utilities For J-Link
If you want to use the dedicated flash programming utilities for commercial and production pur- poses, you need to obtain a license from SEGGER. SEGGER also offers to create ded- icated flash programming utilities for custom hardware. When starting a dedicated...
Page 90: Supported Flash Memories
If you want to use dedicated flash programming utilities for production and commer- cial purposes you need to obtain a license from SEGGER. In order to obtain a license for a dedicated flash programming utility, there are two options: •...
Page 91: F.a.q
Q: I want to use the dedicated flash programming utilities with my own hardware. Is that possible? A: The free dedicated flash programming utilities which come with J-Link do not support custom hardware.mIn order to use your own hardware with a dedicated...
Page 92: Additional Software Packages In Detail
The J-Link Software Developer Kit is needed if you want to write your own program with J-Link / J-Trace. The J-Link DLL is a standard Windows DLL typically used from C programs (Visual Basic or Delphi projects are also possible). It makes the entire...
Page 93: Using The J-Linkarm.dll
What is the JLinkARM.dll? The J-LinkARM.dll is a standard Windows DLL typically used from C or C++, but also Visual Basic or Delphi projects. It makes the entire functionality of the J-Link / J- Trace available through the exported functions.
Page 94: Determining The Version Of Jlinkarm.dll
Process Explorer. It shows you details about the DLLs, used by your program, such as manufacturer and version. Process Explorer is - at the time of writing - a free utility which can be downloaded from www.sysinternals.com. J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 95: Working With J-Link And J-Trace
Chapter 5 Working with J-Link and J-Trace This chapter describes functionality and how to use J-Link and J-Trace. J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 96: Connecting The Target System
5.1.2 Verifying target device connection If the USB driver is working properly and your J-Link / J-Trace is connected with the host system, you may connect J-Link / J-Trace to your target hardware. Then start JLink.exe which should now display the normal J-Link / J-Trace related information and in addition to that it should report that it found a JTAG target and the target’s...
Page 97: Indicators
5.2.1 Main indicator For J-Links up to V7, the main indicator is single color (Green). J-Link V8 comes with a bi-color indicator (Green & Red LED), which can show multiple colors: green, red and orange.
Page 98 GREEN, constant Emulator has enumerated and is in Idle mode. GREEN, switched off for J-Link heart beat. Will be activated after the emulator 10ms once per second has been in idle mode for at least 7 seconds. Emulator has a fatal error. This should not normally hap- GREEN, flashing at 1 Hz pen.
Page 99: Input Indicator
5.2.2 Input indicator Some newer J-Links such as the J-Link Pro/Ultra come with additional input/output Indicators. The input indicator is used to give the user some information about the status of the target hardware. 5.2.2.1 Bi-color input indicator Indicator status...
Page 100: Jtag Interface
IAR C-SPY® debugger, ARM’s AXD using RDI, a flash programming appli- cation such as SEGGER’s J-Flash, or any other application using J-Link / J-Trace. It is the application’s responsibility to supply a way to configure the scan chain. Most applications offer a dialog box for this purpose.
Page 101 SEGGER J-Flash configuration dialog This dialog box can be found at Options|Project settings. J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 102 This dialog can be found under RDI|Configure for example in IAR Embedded Work- bench®. For detailed information check the IAR Embedded Workbench user guide. IAR J-Link configuration dialog box This dialog box can be found under Project|Options. J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 103: Determining Values For Scan Chain Configuration
If only one device is connected to the scan chain, the default configuration can be used. In other cases, J-Link / J-Trace may succeed in automatically recognizing the devices on the scan chain, but whether this is possible depends on the devices present on the scan chain.
Page 104: Jtag Speed
JTAG interface. If you use the adaptive clocking feature, transmission delays, gate delays, and syn- chronization requirements result in a lower maximum clock frequency than with non- adaptive clocking. J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 105: Swd Interface
Table 5.6: J-Link supported SWO input speeds 5.4.2.2 Configuring SWO speeds The max. SWO speed in practice is the max. speed which both, target and J-Link can handle. J-Link can handle the frequencies described in SWO on page 105 whereas the max.
Page 106 Example 2 Target CPU running at 10 MHz. Possible SWO output speeds are: 10MHz, 5MHz, 3.33MHz, ... J-Link V7: Supported SWO input speeds are: 6MHz / n, n>= 1: 6MHz, 3MHz, 2MHz, 1.5MHz, ... Permitted combinations are: SWO output SWO input...
Page 107: Multi-Core Debugging
Multi-core debugging J-Link / J-Trace is able to debug multiple cores on one target system connected to the same scan chain. Configuring and using this feature is described in this section. 5.5.1 How multi-core debugging works Multi-core debugging requires multiple debuggers or multiple instances of the same debugger.
Page 108: Using Multi-Core Debugging In Detail
Working with J-Link and J-Trace 5.5.2 Using multi-core debugging in detail Connect your target to J-Link / J-Trace. Start your debugger, for example IAR Embedded Workbench for ARM. Choose Project|Options and configure your scan chain. The picture below shows the configuration for the first ARM core on your target.
Page 109: Things You Should Be Aware Of
JTAG speeds. For example: Core #1: 2MHz maximum JTAG speed Core #2: 4MHz maximum JTAG speed Scan chain: 2MHz maximum JTAG speed J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 110 All cores share the same RESET line. You should be aware that resetting one core through the RESET line means resetting all cores which have their RESET pins con- nected to the RESET line on the target. J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 111: Connecting Multiple J-Links / J-Traces To Your Pc
The product id (PID) for J-Link / J-Trace #2 is 102 and so on. A different PID means that J-Link / J-Trace is identified as a different device, requir- ing a new driver. The driver for a new J-Link device will be installed automatically.
Page 112: Configuring Multiple J-Links / J-Traces
12. you can verify the driver installation by consulting the Windows device manager. If the driver is installed and your J-Link / J-Trace is connected to your computer, the device manager should list the J-Link USB drivers as a node below "Universal Serial Bus controllers"...
Page 113: Connecting To A J-Link / J-Trace With Non Default Usb-Address
Connecting to a J-Link / J-Trace with non default USB- Address Restart JLink.exe and type usb 1 to connect to J-Link / J-Trace #1. You may connect other J-Links / J-Traces to your PC and connect to them as well. To connect to an unconfigured J-Link / J-Trace (with default address "0"), restart...
Page 114: J-Link Control Panel
J-Link features such as flash download, flash breakpoints and ARM instruction set simulation. The J-Link control panel win- dow can be accessed via the J-Link tray icon in the tray icon list. This icon is available when the debug session is started.
Page 115 Section: Flash download In this section, settings for the use of the J-Link ARM FlashDL feature and related settings can be configured. When a license for J-Link ARM FlashDL is found, the color indicator is green and "License found" appears right to the J-Link FlashDL usage settings.
Page 116 Save settings: When this button is pushed, the current settings in the Settings tab will be saved in a configuration file. This file is created by J-Link and will be created for each project and each project configuration (e.g. Debug_RAM, Debug_Flash).
Page 117 Note: It is possible for the debugger to bypass the breakpoint functionality of the J-Link software by writing to the debug registers directly. This means for ARM7/ ARM9 cores write accesses to the ICE registers, for Cortex-M3 devices write accesses to the memory mapped flash breakpoint registers and in general simple write accesses for software breakpoints (if the program is located in RAM).
Page 118 In this section the name and the value of the CPU registers are shown. 5.7.1.6 Target Power In this section currently just the power consumption of the target hardware is shown. J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 119 In this section SWV information are shown. • Status: Shows the encoding and the baudrate of the SWV data received by the target (Manchester/UART, currently J-Link only supports UART encoding). • Bytes in buffer: Shows how many bytes are in the DLL SWV data buffer.
Page 120: Reset Strategies
Some CPUs can actually be halted before executing any instruction, because the start of the CPU is delayed after reset release. If a pause has been specified, J-Link waits for the specified time before trying to halt the CPU. This can be useful if a bootloader which resides in flash or ROM needs to be started after reset.
Page 121 No reset is performed. Nothing happens. 5.8.1.5 Type 4: Hardware, halt with WP The hardware RESET pin is used to reset the CPU. After reset release, J-Link continu- ously tries to halt the CPU using a watchpoint. This typically halts the CPU shortly after reset release;...
Page 122: Strategies For Cortex-M Devices
CPU after the reset. 5.8.2.1 Type 0: Normal This is the default strategy. It works well for most Cortex-M devices. J-Link tries to reset both, core and peripherals by setting the SYSRESETREQ & VECTRESET bits in the AIRCR. The VC_CORERESET bit is used to halt the CPU before it executes a single instruction.
Page 123 CPU immediately after reset. After the CPU is halted, the watchdog is disabled, since the watchdog is running after reset by default and if the target appli- cation does not feed the watchdog, J-Link loses connection to the device since it is reset permanently.
Page 124: Using Dcc For Memory Access
This DCC handler typically requires less than 1 µs per call. The DCC handler, as well as the optional DCC abort handler, is part of the J-Link soft- ware package and can be found in the Samples\DCC\IAR directory of the package.
Page 125: J-Link Script Files
Currently this function is only used to configure if the target which is connected to J-Link has an ETB or not. For more information how to configure the existence of an ETB, please refer to Global DLL variables on page 128.
Page 126 Before calling this function, please make sure that the JTAG chain has been config- ured correctly by setting the appropriate global DLL variables. For more information about the known global DLL variables, please refer to Global DLL variables on page 128. J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 127 NumBits); 5.10.2.11JTAG_Store() Description Stores a JTAG seuqnece (max. 64 bits per pin) in the DLL JTAG buffer. Prototype __api__ int JTAG_Store(unsigned __int64 tms, unsigned __int64 tdi, int NumBits); J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 128: Global Dll Variables
JTAG chain), which is lost at a TAP reset. Prototype __api__ int JTAG_Reset(void); 5.10.2.16SYS_Sleep() Description Waits for a given number of miliseconds. During this time, J-Link does not communi- cate with the target. Prototype __api__ int SYS_Sleep(int Delayms); 5.10.3 Global DLL variables The script file feature also provides some global variables which are used for DLL configuration.
Page 129 Description Used to set the target CPU core. If auto-detec- tion of the device is not possible, you have to set this variable to tell J-Link what CPU core is connected to it. This variable can only be set Write-only to a known Global J-Link DLL constant.
Page 130: Global Dll Constants
SYS_Sleep(5); // Give pin some time to get low JTAG_TRSTPin = 1; If the connected device has an ETB and you want to use it with J-link, this variable should be set to 1. Setting this variable in another function as InitEmu() does not have any Write-only effect.
Page 131: Script File Language
CORTEX_R4 5.10.5 Script file language The syntax of the J-Link script file language follows the conventions of the C-lan- guage, but it does not support all expresisons and operators which are supported by the C-language. In the following, the supported operators and expressions are listed.
Page 132: Executing J-Link Script Files
To execute a script file out of your debugger IDE, simply select the script file to exe- cute in the Settings tab of the J-Link control panel and click the save button (after the debug session has been started). Usually a project file for J-Link is set by the debugger, which allows the J-Link DLL to save the settings of the control panel in this project file.
Page 133: Command Strings
5.11 Command strings The behavior of the J-Link can be customized via command strings passed to the JLinkARM.dll which controls J-Link. Applications such as the J-Link Commander, but also the C-SPY debugger which is part of the IAR Embedded Workbench, allow pass- ing one or more command strings.
Page 134 To avoid stalling the debug session, a critical memory area can be excluded from access: J-Link will not try to read or write to critical memory areas and instead ignore the access silently. Some debuggers (such as IAR C-SPY) can try to access memory in such areas by dereferencing non-initialized pointers even if the debugged program (the debuggee) is working perfectly.
Page 135 0x40008000-0x7FCFFFFF Reserved 0x7FD02000-0x7FD02000 Reserved 0x80000000-0xDFFFFFFF Reserved To exclude these areas from being accessed through J-Link the map exclude com- mand should be used as follows: map exclude 0x00080000-0x3FFFFFFF map exclude 0x40008000-0x7FCFFFFF map exclude 0x7FD02000-0x7FD02000 map exclude 0x80000000-0xDFFFFFFF 5.11.1.7 map indirectread This command can be used to read a memory area indirectly.
Page 136 Note that if this check is turned off (SetCheckModeAfterRead = 0), the success of read operations cannot be verified anymore and possible data aborts are not recognized. J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 137 SetResetPulseLen = 50 5.11.1.13 SetResetType This command selects the reset startegy which shall be used by J-Link, to reset the device. The value which is used for this command is analog to the reset type which shall be selected. For a list of all reset types which are available, please refer to Reset strategies on page 120.
Page 138 Working with J-Link and J-Trace 5.11.1.16 SetSysPowerDownOnIdle When using this command, the target CPU is powered-down when no transmission between J-Link and the target CPU was performed for a specific time. When the next command is given, the CPU is powered-up. Note: This command works only for Cortex-M3 devices.
Page 139: Using Command Strings
5.11.2 Using command strings 5.11.2.1 J-Link Commander The J-Link command strings can be tested with the J-Link Commander. Use the com- mand exec supplemented by one of the command strings. Example exec SupplyPower = 1 exec map reset exec map exclude 0x10000000-0x3FFFFFFF 5.11.2.2 IAR Embedded Workbench...
Page 140 On the Extra Options page, select Use command line options. Enter --jlink_exec_command "<CommandLineOption>" in the textfield, as shown in the screenshot below. If more than one command should be used separate the com- mands with semicolon. J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 141: Switching Off Cpu Clock During Debug
In this case, the CPU will stop at the first instruction in the ISR (typically at address 0x18). J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 142: Cache Handling
Because ARM7 cores have a unified cache, there is no need to handle the caches dur- ing debug. 5.13.4 Cache handling of ARM9 cores ARM9 cores with cache require J-Link / J-Trace to handle the caches during debug. If the processor enters debug state with caches enabled, J-Link / J-Trace does the fol- lowing:...
Page 143: Flash Download And Flash Breakpoints
Chapter 6 Flash download and flash break- points This chapter describes how flash download and flash breakpoints with J-Link work. In addition to that it contains a list of supported microcontrollers for J-Link. J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 144: Introduction
The JLinkARM.dll is able to use the flash download and flash breakpoints features. Only the flash breakpoints feature requires an additional license. For more informa- tion about flash download and flash breakpoints, please refer to J-Link RDI User’s Guide (UM08004), chapter Flash download and chapter Breakpoints in flash memory.
Page 145: Licensing
Some J-Links are available with device-based licenses for flash download or flash breakpoints, but the standard J-Link does not come with a built-in license. You will need to obtain a license for every J-Link. For more information about the different license types, please refer to License types on page 50.
Page 146 Flash download and flash breakpoints Now choose Add license to add one or more new licenses. Enter your license(s) and choose OK. Now the licenses should have been added. J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 147: Supported Devices
Supported devices J-Link supports download into the internal flash of a large number of microcontrol- lers. You can always find the latest list of supported devices on our website: http://www.segger.com/supported-devices.html In general, J-Link can be used with any ARM7/9/11, Cortex-M0/M1/M3/M4 and Cor- tex-A5/A8/R4 core even if it does not provide internal flash.
Page 148: Setup For Different Debuggers (Internal Flash)
>Download has to be disabled, as shown below. If you use the IAR project for the first time, the use of J-Link ARM FlashDL and FlashBPs is set to Auto, which is the default value. For more information about dif-...
Page 149: Keil Mdk
Currently changes in this tab will take effect next time the debug session is started. 6.4.2 Keil MDK To use the J-Link ARM FlashDL and FlashBP features with the Keil MDK is quite sim- ple: First, choose the device in the project settings if not already done. The device set- tings can be found at Project->Options for Target->Device.
Page 150 CHAPTER 6 Flash download and flash breakpoints Then J-Link / J-Trace has to be selected as debugger. To select J-Link / J-Trace as debugger simply choose J-Link / J-Trace from the list box which can be found at Project->Options for Target->Debug.
Page 151: J-Link Gdb Server
J-Link status window. When the debug session is running you can modify the set- tings regarding J-Link ARM FlashDL and FlashBPs, in the Settings tab and save them in the settings file. 6.4.3 J-Link GDB Server The configuration for the J-Link GDB Server is done by the .gdbinit file. The follow- ing commands has to be added to the .gdbinit file to enable download into internal...
Page 152: Setup For Different Debuggers (Cfi Flash)
Using the J-Link flash download and flash breakpoints features with the IAR Embed- ded Workbench is quite simple: First, start the debug session and open the J-Link Control Panel. In the tab "Settings" you will find the location of the settings file.
Page 153: J-Link Gdb Server
6.5.2 J-Link GDB Server The configuration for the J-Link GDB Server is done by the .gdbinit file. The follow- ing commands has to be added to the .gdbinit file to enable J-Link ARM FlashDL and FlashBPs: monitor WorkRAM = <SAddr>-<EAddr>...
Page 154 CHAPTER 6 Flash download and flash breakpoints J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 155: Device Specifics
Chapter 7 Device specifics This chapter gives some additional information about specific devices. J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 156: Analog Devices
CHAPTER 7 Device specifics Analog Devices J-Link has been tested with the following MCUs from Analog Devices, but should work with any ARM7/9 and Cortex-M3 device: • ADuC7020x62 • ADuC7021x32 • ADuC7021x62 • ADuC7022x32 • ADuC7022x62 • ADuC7024x62 • ADuC7025x32 •...
Page 157 • Analog ADuC7128 • Analog ADuC7129 • Analog ADuC7229x126 J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 158: Atmel
CHAPTER 7 Device specifics ATMEL J-Link has been tested with the following ATMEL devices, but should work with any ARM7/9 and Cortex-M3 device: • AT91SAM7A3 • AT91SAM7S32 • AT91SAM7S321 • AT91SAM7S64 • AT91SAM7S128 • AT91SAM7S256 • AT91SAM7S512 • AT91SAM7SE32 •...
Page 159 In order to work with an ATMEL AT91SAM7 device, it has to be initialized. The follow- ing paragraph describes the steps of an init sequence. An example for different soft- ware tools, such as J-Link GDB Server, IAR Workbench and RDI, is given. •...
Page 160: At91Sam9
J-Link. 7.2.2.1 JTAG settings We recommend using adaptive clocking. This information is applicable to the following devices: • AT91RM9200 • AT91SAM9260 • AT91SAM9261 • AT91SAM9262 • AT91SAM9263 J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 161: Freescale
If your device has been locked by setting the MCU security status to "secure", and mass erase via debug interface is not disabled, J-Link is able to unlock your Kinetis K40/K60 device. The device can be unlocked by using the "unlock" comnmand in J- Link Commander.
Page 162: Luminary Micro
CHAPTER 7 Device specifics Luminary Micro J-Link has been tested with the following Luminary Micro devices, but should work with any ARM7/9 and Cortex-M3 device: • LM3S101 • LM3S102 • LM3S301 • LM3S310 • LM3S315 • LM3S316 • LM3S317 •...
Page 163: Unlocking Lm3Sxxx Devices
If your device has been "locked" accidentially (e.g. by bad application code in flash which mis-configures the PLL) and J-Link can not identify it anymore, there is a spe- cial unlock sequence which erases the flash memory of the device, even if it can not be identified.
Page 164: Nxp
CHAPTER 7 Device specifics J-Link has been tested with the following NXP devices, but should work with any ARM7/9 and Cortex-M3 device: • LPC1111 • LPC1113 • LPC1311 • LPC1313 • LPC1342 • LPC1343 • LPC1751 • LPC1751 • LPC1752 •...
Page 165: Lpc
Indirectly reading solves the fast GPIO problem, because only direct regis- ter access corrupts the register contents. Define a 256 byte aligned area in RAM of the LPC target device with the J-Link com- mand map ram and define afterwards the memory area which should be read indirect with the command map indirectread to use the indirectly reading feature of J-Link.
Page 166 PC (R15) manually, after reset in order to debug the application. LPC288x flash programming In order to use the LPC288x devices in combination with J-Link FlashDL the applica- tion you are trying to debug, should be linked to the original flash @ addr 0x10400000.
Page 167: Oki
J-Link has been tested with the following OKI devices, but should work with any ARM7/9 and Cortex-M3 device: • ML67Q4002 • ML67Q4003 • ML67Q4050 • ML67Q4051 • ML67Q4060 • ML67Q4061 If you experience problems with a particular device, do not hesitate to contact Seg- ger.
Page 168: Samsung
CHAPTER 7 Device specifics Samsung J-Link has been tested with the following Samsung devices, but should work with any ARM7/9 and Cortex-M device: • S3FN60D If you experience problems with a particular device, do not hesitate to contact Seg- ger.
Page 169: St Microelectronics
ST Microelectronics J-Link has been tested with the following ST Microelectronics devices, but should work with any ARM7/9 and Cortex-M3 device: • STR710FZ1 • STR710FZ2 • STR711FR0 • STR711FR1 • STR711FR2 • STR712FR0 • STR712FR1 • STR712FR2 • STR715FR0 •...
Page 170: Str 71X
All devices of this family are supported by J-Link. 7.8.4.1 Flash erasing The devices have 3 TAP controllers built-in. When starting J-Link.exe, it reports 3 JTAG devices. A special tool, J-Link STR9 Commander (JLinkSTR91x.exe) is available to directly access the flash controller of the device. This tool can be used to erase the flash of the controller even if a program is in flash which causes the ARM core to stall.
Page 171 CPU is in debug mode (e.g. halted by J-Link). This can be config- ured via the DBGMCU_CR register of the STM32F devices. To configure the watchdog...
Page 172: Texas Instruments
CHAPTER 7 Device specifics Texas Instruments J-Link has been tested with the following Texas Instruments devices, but should work with any ARM7/9 and Cortex-M3 device: • TMS470R1A64 • TMS470R1A128 • TMS470R1A256 • TMS470R1A288 • TMS470R1A384 • TMS470R1B512 • TMS470R1B768 •...
Page 173: Target Interfaces And Adapters
Chapter 8 Target interfaces and adapters This chapter gives an overview about J-Link / J-Trace specific hardware details, such as the pinouts and available adapters. J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 174: 20-Pin Jtag/Swd Connector
RESET pin of the target CPU, which is typically called "nRST", "nRESET" or "RESET". This pin is not connected in J-Link. It is reserved for com- patibility with other equipment to be used as a debug DBGRQ request signal to the target system. Typically connected to DBGRQ if available, otherwise left open.
Page 175 Pins 4, 6, 8, 10, 12, 14, 16, 18, 20 are GND pins connected to GND in J-Link. They should also be connected to GND in the target system. 8.1.1.1 Target board design We strongly advise following the recommendations given by the chip manufacturer.
Page 176: Pinout For Swd
Not con- This pin is not connected in J-Link. nected This pin is not used by J-Link. If the device may also be Not Used NC accessed via JTAG, this pin may be connected to nTRST, otherwise leave open.
Page 177 178. Table 8.3: J-Link / J-Trace SWD pinout Pins 4, 6, 8, 10, 12, 14, 16, 18, 20 are GND pins connected to GND in J-Link. They should also be connected to GND in the target system. J-Link / J-Trace (UM08001)
Page 178 Pin 19 of the connector can be used to supply power to the target hardware. Supply voltage is 5V, max. current is 300mA. The output current is monitored and protected against overload and short-circuit. Power can be controlled via the J-Link commander. The following commands are available to control power: Command...
Page 179: 38-Pin Mictor Jtag And Trace Connector
Target board Target board Target board Target board Target board Trace JTAG Trace JTAG Trace JTAG connector connector connector connector connector connector Target board Target board Target board J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 180: Pinout
Trace signal. For more information, please refer to Trace signal 10 Assignment of trace information pins between ETM archi- tecture versions on page 182. nTRST Active-low JTAG reset Table 8.5: JTAG+Trace connector pinout J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 181 Trace signal 16 Trace signal 4 Trace signal 15 Trace signal 3 Trace signal 14 Trace signal 2 Trace signal 13 Trace signal 1 Table 8.5: JTAG+Trace connector pinout J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 182: Assignment Of Trace Information Pins Between Etm Architecture Versions
TRACE- CLK. Parameter Min. Max. Explanation Tperiod 1000ns Clock period Fmax 1MHz 200MHz Maximum trace frequency 2.5ns High pulse width 2.5ns Low pulse width Table 8.7: Clock frequency J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 183 J-Trace supports half-rate clocking mode. Data is output on each edge of the TRACECLK signal and TRACECLK (max) <= 100MHz. For half-rate clocking, the setup and hold times at the JTAG+Trace connector must be observed. J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 184: 19-Pin Jtag/Swd And Trace Connector
Typically connected to TDI of the target CPU. For CPUs Output which do not provide TDI (SWD-only devices), this pin is not used. J-Link will ignore the signal on this pin when using SWD. Not connected inside J-Link. Leave open on target hard- ware.
Page 185: Target Power Supply
Pins 11 and 13 of the connector can be used to supply power to the target hardware. Supply voltage is 5V, max. current is 300mA. The output current is monitored and protected against overload and short-circuit. Power can be controlled via the J-Link commander. The following commands are available to control power: Command...
Page 186: 9-Pin Jtag/Swd Connector
Typically connected to TDI of the target CPU. For CPUs Output which do not provide TDI (SWD-only devices), this pin is not used. J-Link will ignore the signal on this pin when using SWD. Not connected inside J-Link. Leave open on target hard- ware.
Page 187: Adapters
Adapters There are various adapters available for J-Link as for example the JTAG isolator, the J-Link RX adapter or the J-Link Cortex-M adapter. For more information about the different adapters, please refer to http://www.segger.com/jlink-adapters.html. J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 188 CHAPTER 8 Target interfaces and adapters J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 189: Background Information
ARM9 architecture is based on Reduced Instruction Set Computer (RISC) principles. The instruction set and the related decode mechanism are greatly simplified com- pared with microprogrammed Complex Instruction Set Computer (CISC). J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 190: Jtag
The instruction register holds the current instruction and its content is used by the TAP controller to decide which test to perform or which data register to access. It consist of at least two shift-register cells. J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 191: The Tap Controller
Data may be loaded in parallel to the selected test data registers. Shift-DR The test data register connected between TDI and TDO shifts data one stage towards the serial output with each clock. J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 192 Once latched, this new instruction becomes the cur- rent one. The parallel latch prevents changes at the parallel output of the instruction register from occurring during the shifting process. J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 193: Embedded Trace Macrocell (Etm)
In the following a sample integration of J-Trace and the trace functionality on the debugger side is shown. The sample is based on IAR’s Embedded Workbench for ARM integration of J-Trace. J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 194 CHAPTER 9 Background information 9.2.3.1 Code coverage - Disassembly tracing J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 195 9.2.3.2 Code coverage - Source code tracing J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 197: Embedded Trace Buffer (Etb)
No additional special trace port is required, so that the ETB can be read via J-Link. The trace functionality via J-Link is limited by the size of the ETB. While capturing runs, the trace information in the buffer will be overwritten every time the buffer size has been reached.
Page 198: Flash Programming
Background information Flash programming J-Link / J-Trace comes with a DLL, which allows - amongst other functionalities - reading and writing RAM, CPU registers, starting and stopping the CPU, and setting breakpoints. The standard DLL does not have API functions for flash programming.
Page 199 RDI, (Remote debug interface) is a standard for "debug transfer agents" such as J- Link. It allows using J-Link from any RDI compliant debugger. RDI by itself does not include download to flash. To debug in flash, you need to somehow program your application program (debuggee) into the flash.
Page 200: J-Link / J-Trace Firmware
Every time you connect to J-Link / J-Trace, JLinkARM.dll checks if its embedded firm- ware is newer than the one used the J-Link / J-Trace. The DLL will then update the firmware automatically. This process takes less than 3 seconds and does not require a reboot.
Page 201 JLinkARM.dll. This automatically replaces the invalidated firmware with its embedded firmware. In the screenshot: • The red box identifies the new firmware. • The green box identifies the old firmware which has been replaced. J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 203: Designing The Target Board For Trace
Chapter 10 Designing the target board for trace This chapter describes the hardware requirements which have to be met by the tar- get board. J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 204: Overview Of High-Speed Board Design
The decision is related to track length between the ASIC and the JTAG+Trace connector, see Terminating the trace signal on page 205 for further ref- erence. J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 205: Terminating The Trace Signal
Care must be taken not to connect devices in this way, unless the distor- tion does not affect device operation. J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 206: Signal Requirements
Fmax 200MHz Ts setup time (min.) 2.0ns Th hold time (min.) 1.0ns TRACECLK high pulse width (min.) 1.5ns TRACECLK high pulse width (min.) 1.5ns Table 10.1: Signal requirements J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 207: Support And Faqs
Support and FAQs This chapter contains troubleshooting tips together with solutions for common prob- lems which might occur when using J-Link / J-Trace. There are several steps you can take before contacting support. Performing these steps can solve many problems and often eliminates the need for assistance.
Page 208: Measuring Download Speed
USB 2.0 port • USB 2.0 hub • J-Link • Target with ARM7 running at 50MHz. Below is a screenshot of JLink.exe after the measurement has been performed. J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 209: Troubleshooting
12. Start JLink.exe . 13. If JLink.exe displays the J-Link / J-Trace serial number and the target proces- sor’s core ID, the J-Link / J-Trace is working properly and cannot be the cause of your problem. 14. If JLink.exe is unable to read the target processor’s core ID you should analyze the communication between your target and J-Link / J-Trace with a logic analyzer or oscilloscope.
Page 210 CHAPTER 11 Support and FAQs J-Link/J-Trace does not get any connection to the target Most likely reasons: a.) The JTAG cable is defective. b.) The target hardware is defective. Remedy: Follow the steps described in General procedure on page 209.
Page 211: Signal Analysis
J-Link / J-Trace and the target device. 11.3.1 Start sequence This is the signal sequence output by J-Link / J-Trace at start of JLink.exe . It should be used as reference when tracing potential J-Link / J-Trace related hardware prob- lems.
Page 212: Contacting Support
General procedure on page 209. You may also try your J-Link / J-Trace with another PC and if possible with another target system to see if it works there. If the device functions correctly, the USB setup on the original machine or your target hardware is the source of the problem, not J-Link / J-Trace.
Page 213: Frequently Asked Questions
Can J-Link / J-Trace read back the status of the JTAG pins? Yes, the status of all pins can be read. This includes the outputs of J-Link / J-Trace as well as the supply voltage, which can be useful to detect hardware problems on the target system.
Page 214 Registers on ARM 7 / ARM 9 targets I’m running J-Link.exe in parallel to my debugger, on an ARM 7 target. I can read memory okay, but the processor registers are different. Is this normal? If memory on an ARM 7/9 target is read or written the processor registers are modified.
Page 215: Glossary
Chapter 12 Glossary This chapter describes important terms used throughout this manual. J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 216 Glossary Adaptive clocking A technique in which a clock signal is sent out by J-Link / J-Trace. J-Link / J-Trace waits for the returned clock before generating the next clock pulse. The technique allows the J-Link / J-Trace interface unit to adapt to differing signal drive capabilities and differing cable lengths.
Page 217 Open collector A signal that may be actively driven LOW by one or more drivers, and is otherwise passively pulled HIGH. Also known as a "wired AND" signal. J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 218 The electronic clock signal which times data on the TAP data lines TMS, TDI, and TDO. The electronic signal input to a TAP controller from the data source (upstream). Usu- ally, this is seen connecting the J-Link / J-Trace Interface Unit to the first TAP control- ler. J-Link / J-Trace (UM08001)
Page 219 The electronic signal output from a TAP controller to the data sink (downstream). Usually, this is seen connecting the last TAP controller to the J-Link / J-Trace Inter- face Unit. Test Access Port (TAP) The port used to access a device's TAP Controller. Comprises TCK, TMS, TDI, TDO, and nTRST (optional).
Page 221: Literature And References
Chapter 13 Literature and references This chapter lists documents, which we think may be useful to gain deeper under- standing of technical details. J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 222 [RVI] Trace User Guide, ARM DUI ments on the target side. 0155C It is publicly available from ARM ( www.arm.com ). Table 13.1: Literature and References J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 223 Remapping ........218 Remote Debug Interface (RDI) .....218 RESET ..........217 J-Flash ARM ........86 RTCK ..........218 J-Link RTOS ..........218 Adapters ........187 Developer Pack DLL ......92 Supported chips ....... 144–145 J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...
Page 224 TCK .......... 174, 218 TDI .......... 174, 218 TDO ......... 174, 219 Test Access Port (TAP) ......219 Transistor-transistor logic (TTL) ... 219 Watchpoint ........219 Word ..........219 J-Link / J-Trace (UM08001) © 2004-2011 SEGGER Microcontroller GmbH & Co. KG...

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J-trace

Segger J-Link User Manual

1 Introduction

2 Licensing

3 Setup

4 Link and J-Trace Related Software

5 Working with J-Link and J-Trace

6 Flash Download and Flash Breakpoints

7 Device Specifics

8 Target Interfaces and Adapters

9 Background Information

10 Designing the Target Board for Trace

11 Support and Faqs

12 Glossary

13 Literature and References

Quick Links

Troubleshooting

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Summary of Contents for Segger J-Link