Switching Off Cpu Clock During Debug - Segger J-Link User Manual

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Switching off CPU clock during debug

We recommend not to switch off CPU clock during debug. However, if you do, you should
consider the following:
Non-synthesizable cores (ARM7TDMI, ARM9TDMI, ARM920, etc.)
With these cores, the TAP controller uses the clock signal provided by the emulator, which
means the TAP controller and ICE-Breaker continue to be accessible even if the CPU has
no clock.
Therefore, switching off CPU clock during debug is normally possible if the CPU clock is
periodically (typically using a regular timer interrupt) switched on every few ms for at least
a few us. In this case, the CPU will stop at the first instruction in the ISR (typically at
address 0x18).
Synthesizable cores (ARM7TDMI-S, ARM9E-S, etc.)
With these cores, the clock input of the TAP controller is connected to the output of a three-
stage synchronizer, which is fed by clock signal provided by the emulator, which means
that the TAP controller and ICE-Breaker are not accessible if the CPU has no clock.
If the RTCK signal is provided, adaptive clocking function can be used to synchronize the
JTAG clock (provided by the emulator) to the processor clock. This way, the JTAG clock is
stopped if the CPU clock is switched off.
If adaptive clocking is used, switching off CPU clock during debug is normally possible if
the CPU clock is periodically (typically using a regular timer interrupt) switched on every
few ms for at least a few us. In this case, the CPU will stop at the first instruction in the
ISR (typically at address 0x18).
J-Link / J-Trace (UM08001)
CHAPTER 5
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Switching off CPU clock during debug