Dsp Circuit - Orban OPTIMOD 6300 Operating Manual

6-10
TECHNICAL DATA

DSP Circuit

right analog output connectors. These analog signals can represent either the
transmitter or monitor output of audio processing.
Component-Level Description:
IC201 and associated components filter the left channel signal emerging from
IC211. The purpose of these stages is to reduce the out-of-band noise energy
resulting from the delta-sigma D/A's noise-shaping filter and to translate the
differential output of the D/A converter into single-ended form. These com-
ponents apply a 3
This filter does not induce significant overshoot of the processed audio, which
would otherwise waste modulation.
IC212 and associated components form a low-frequency servo amplifier to re-
move residual DC from the signal. The 0.1Hz
induced overshoot in the processed audio.
The buffered output of IC201 is applied to IC213, a balanced output line
driver. This driver emulates a floating transformer; its differential output level
is independent of whether one side of its output is floating or grounded.
IC213 and its right channel counterpart IC214 are socketed for easy field re-
placement. All other circuitry is surface-mounted.
The corresponding right channel circuitry is functionally identical to that just
described.
3. Digital Sample Rate Converter (SRC) and Output Transmitter
Located on input/output/DSP board
Output sample rate converter (SRC) chips IC400 and IC402 convert the 48 kHz
6300 system sample rate to any of the standard 32 kHz, 44.1 kHz, 48 kHz, 88.2
kHz, and 96 kHz rates for the 6300's Digital Out 1 and Digital Out 2 respectively.
The sample rate converters drive digital audio interface transmitters IC403, IC404,
which encode digital audio signals using the AES3 interface format (AES3-1992).
These chips are surface-mounted and are not field-replaceable.
The DSP circuit consists of four Motorola DSP56367 24-bit fixed-point DSP chips,
which execute DSP software code to implement digital signal processing algorithms.
The algorithms filter, compress, and limit the audio signal. The four DSP chips, each
operating at approximately 150 million instructions per second (MIPS), for a total of
600 MIPS, provide the necessary signal processing. A sampling rate of 48 kHz is used.
System initialization normally occurs when power is first applied to the 6300 and can
occur abnormally if the 6300's watchdog timer forces the SC520 to reboot. Upon ini-
tialization, the SC520 CPU downloads the DSP executable code stored in the flash
memory. This typically takes about 7 seconds. Once a DSP chip begins executing its
program, execution is continuous. The SC520 provides the DSP program with pa-
rd
order low-pass filter to the differential signal from the D/A.
ORBAN MODEL 6300
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3 dB frequency prevents tilt-