Dsp Circuit - Orban OPTIMOD-FM 5500 Operation Manual

6-12
TECHNICAL DATA

DSP Circuit

Component-Level Description:
We will describe the signal path for composite 1 output; the signal path for
composite 2 output is exactly analogous. IC401 is a dual-channel high-speed
D/A converter chip that receives the digital composite signal at a 170.66
(512/3) kHz sample rate. Its differential outputs drive current-to-voltage con-
verter amplifier IC403, which drives differential amplifier IC405A. IC405A re-
moves common-mode noise from the D/A output.
IC405B is a DC servo amplifier that removes DC offsets from the D/A output
without introducing significant amounts of low frequency tilt to the compos-
ite waveform.
IC405A drives a third-order passive LC reconstruction filter C9, C10, L9, R17,
R18, on the Composite/SCA daughterboard. (This filter is equalized and phase-
corrected in DSP to obtain excellent flatness and phase-linearity. This opti-
mizes stereo separation.) The resulting signal is a filtered analog representa-
tion of the composite signal generated by the DSP. IC2B buffers this signal
and sums it with the SCA signals from SCA INPUT buffer IC1. Any contribution
from the SCA inputs is therefore not indicated on the
ter displayed by the 5500, because this meter indicates only the composite sig-
nal generated by the DSP.
IC2B and IC3 together form a composite high-current buffer amplifier that re-
ceives the output of IC405A and drives the composite output connector J3
through RFI filter L3 and optional 75
The pilot reference D/A converter IC402 receives serial data from the DSP cir-
cuitry. After being buffered and low-pass filtered by IC407B, the resulting 19
kHz sine wave signal is passed to the Composite/SCA daughterboard and can
be connected to J2 through jumper J6.
The composite line driver amplifiers IC3 and IC4 are socketed in through-hole
packages to facilitate field replacement with simple tools. All other compo-
nents are surface-mounted and are not field-replaceable.
The DSP circuit consists of two Freescale DSPB56724AG dual-core 24-bit fixed-point
DSP chips that execute DSP software code to implement digital signal processing al-
gorithms. The chips operate at a core clock frequency of 245.76MHz.
The algorithms filter, compress, and limit the audio signal. Each of the four DSP
cores operates at approximately 250 million instructions per second (MIPS). A sam-
pling rate of 32 kHz and power-of-two multiples thereof, up to 512 kHz, is used. In
stand-alone stereo encoder mode, the minimum sample rate is 64 kHz.
System initialization normally occurs when power is first applied to the 5500 and can
occur abnormally if the 5500's watchdog timer forces the SC520 to reboot. Upon ini-
tialization, the SC520 CPU downloads the DSP executable code stored in the flash
memory. This typically takes about 7 seconds. Once a DSP chip begins executing its
program, execution is continuous. The SC520 provides the DSP program with pa-
C
OMPOSITE

build-out resistor R11.
ORBAN MODEL 5500
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