Power Management
Table 4-4.
System Memory Power States (Sheet 2 of 2)
Self-Refresh
4.1.4
DMI2/PCI Express Link States
Table 4-5.
DMI2/PCI Express* Link States
L0
L1
Note:
L1 is only supported when the DMI2/PCI Express* port is operating as a PCI Express* port.
4.1.5
Intel QuickPath Interconnect States
Table 4-6.
Intel QPI States
L0
L0p
L1
4.1.6
G, S, and C State Combinations
Table 4-7.
G, S and C State Combinations
Global (G)
State
G0
G0
G0
G0
G1
G1
G2
G3
Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families
Datasheet Volume One
State
CKE de-asserted. In this mode, no transactions are executed and the system
memory consumes the minimum possible power. Self refresh modes apply to
all memory channels for the processor.
• IO-MDLL Off: Option that sets the IO master DLL off when self refresh
occurs.
• PLL Off: Option that sets the PLL off when self refresh occurs.
In addition, the register component found on registered DIMMs (RDIMMs) is
complemented with the following power down states:
— Clock Stopped Power Down with IBT-On
— Clock Stopped Power Down with IBT-Off
State
Full on – Active transfer state.
Lowest Active State Power Management (ASPM) - Longer exit latency.
State
Link on. This is the power on active working state,
A lower power state from L0 that reduces the link from full width to half width
A low power state with longer latency and lower power than L0s and is
activated in conjunction with package C-states below C0.
Processor
Sleep
Core
(S) State
(C) State
S0
C0
S0
C1/C1E
S0
C3
S0
C6/C7
S3
Power off
S4
Power off
S5
Power off
N/A
Power off
Description
Description
Description
Processor
System
State
Clocks
Full On
On
Auto-Halt
On
Deep Sleep
On
Deep Power
On
Down
Off, except RTC
Off, except RTC
Off, except RTC
Power off
Description
Full On
Auto-Halt
Deep Sleep
Deep Power Down
Suspend to RAM
Suspend to Disk
Soft Off
Hard off
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