Figure 9-35. Host Terminating An Ultradma Data Out Burst Timing Diagram - AMD Geode SC3200 Data Book

32581C
IDE_DREQ0
(device)
IDE_DACK0#
(host)
IDE_IOW0#
(STOP0#)
(host)
IDE_IORDY0#
(DDMARDY0)#
(device)
IDE_IOR0#
(HSTROBE0#)
(host)
IDE_DATA[15:0]
(host)
IDE_ADDR[2:0]
IDE_CS[0:1]#
Note: The definitions for the IDE_IOW[0:1]# (STOP[0:1]#), IDE_IORDY[0,1]# (DDMARDY[0:1]#) and IDE_IOR[0:1]#
(HSTROBE[0:1]#) signal lines are no longer in effect after IDE_DREQ[0:1] and IDE_DACK[0:1]# are de-asserted.

Figure 9-35. Host Terminating an UltraDMA Data Out Burst Timing Diagram

398
t
LI
t
t
LI
SS
t
LI
t
MLI
t
ACK
t
IORDYZ
t
ACK
t t
DVH
DVS
CR
t
ACK
AMD Geode™ SC3200 Processor Data Book
Electrical Specifications