Table 5-38. Bank Selection Encoding; Table 5-39. Bank 1 Register Map; Table 5-40. Bank 2 Register Map; Table 5-41. Bank 3 Register Map - AMD Geode SC3200 Data Book

32581C
7 6 5
0 x x
1 0 x
1 1 x
1 1 x
1 1 1
1 1 1
Offset Type
00h R/W
01h R/W
02h ---
03h W
R/W
04h-07h ---
1. When bit 7 of this register is set to 1, bits [6:0] of BSR select the bank, as shown in Table 5-38 on page 130.
Offset Type
00h R/W
01h R/W
02h R/W
03h R/W
04h R/W
05h ---
06h RO
07h RO
Offset Type
00h RO
01h RO
02h RO
03h R/W
04h-07h ---
130

Table 5-38. Bank Selection Encoding

BSR Bits
4 3 2
x x x
x x x
x x x
x x x
0 0 0
0 0 1

Table 5-39. Bank 1 Register Map

Name
LBGD(L). Legacy Baud Generator Divisor Port (Low Byte)
LBGD(H). Legacy Baud Generator Divisor Port (High Byte)
RSVD. Reserved
1
LCR . Line Control
1
BSR . Bank Select
RSVD. Reserved

Table 5-40. Bank 2 Register Map

Name
BGD(L). Baud Generator Divisor Port (Low Byte)
BGD(H). Baud Generator Divisor Port (High Byte)
EXCR1. Extended Control1
BSR. Bank Select
EXCR2. Extended Control 2
RSVD. Reserved
RXFLV. RX_FIFO Level
TXFLV. TX_FIFO Level

Table 5-41. Bank 3 Register Map

Name
MRID. Module and Revision ID
SH_LCR. Shadow of LCR
SH_FCR. Shadow of FIFO Control
BSR. Bank Select
RSVD. Reserved
1 0 Bank Selected
x x
x x
1 x
x 1
0 0
0 0
AMD Geode™ SC3200 Processor Data Book
SuperI/O Module
0
1
1
1
2
3