Table 6-20. F2: Pci Header Registers For Ide Controller Support Summary - AMD Geode SC3200 Data Book

32581C

Table 6-20. F2: PCI Header Registers for IDE Controller Support Summary

Width
F2 Index (Bits) Type
00h-01h 16 RO
02h-03h 16 RO
04h-05h 16 R/W
06h-07h 16 RO
08h 8 RO
09h-0Bh 24 RO
0Ch 8 RO
0Dh 8 RO
0Eh 8 RO
0Fh 8 RO
10h-13h 32 RO
14h-17h 32 RO
18h-1Bh 32 RO
1Ch-1Fh 32 RO
20h-23h 32 R/W
24h-2Bh --- ---
2Ch-2Dh 16 RO
2Eh-2Fh 16 RO
30h-3Fh --- ---
40h-43h 32 R/W
44h-47h 32 R/W
48h-4Bh 32 R/W
4Ch-4Fh 32 R/W
50h-53h 32 R/W
54h-57h 32 R/W
58h-5Bh 32 R/W
5Ch-5Fh 32 R/W
60h-FFh --- ---
180
Name
Vendor Identification Register
Device Identification Register
PCI Command Register
PCI Status Register
Device Revision ID Register
PCI Class Code Register
PCI Cache Line Size Register
PCI Latency Timer Register
PCI Header Type Register
PCI BIST Register
Base Address Register 0 (F2BAR0) — Reserved for possible
future use by the Core Logic module.
Base Address Register 1 (F2BAR1) — Reserved for possible
future use by the Core Logic module.
Base Address Register 2 (F2BAR2) — Reserved for possible
future use by the Core Logic module.
Base Address Register 3 (F2BAR3) — Reserved for possible
future use by the Core Logic module.
Base Address Register 4 (F2BAR4) — Sets the base address for
the I/O mapped Bus Master IDE Registers (summarized in Table
6-21)
Reserved
Subsystem Vendor ID
Subsystem ID
Reserved
Channel 0 Drive 0 PIO Register
Channel 0 Drive 0 DMA Control Register
Channel 0 Drive 1 PIO Register
Channel 0 Drive 1 DMA Control Register
Channel 1 Drive 0 PIO Register
Channel 1 Drive 0 DMA Control Register
Channel 1 Drive 1 PIO Register
Channel 1 Drive 1 DMA Control Register
Reserved
Core Logic Module - Register Summary
Reset
Value
100Bh
0502h
0000h
0280h
01h
010180h
00h
00h
00h
00h
00000000h
00000000h
00000000h
00000000h
00000001h
00h
100Bh
0502h
00h
00009172h
00077771h
00009172h
00077771h
00009172h
00077771h
00009172h
00077771h
00h
AMD Geode™ SC3200 Processor Data Book
Reference
(Table 6-35)
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