Figure 9-31. Host Terminating An Ultradma Data In Burst Timing Diagram - AMD Geode SC3200 Data Book

32581C
IDE_DREQ0
(device)
IDE_DACK0#
(host)
IDE_IOW0#
(STOP0#)
(host)
IDE_IOR0#
(HDMARDY0#)
(host)
IDE_IRDY0
(DSTROBE0)
(device)
IDE_DATA[15:0]
(device)
IDE_CS[0:1]#
IDE_ADDR[2:0]
Note: The definitions for the IDE_IOW[0:1]# (STOP[0:1]#), IDE_IOR[0:1]# (HDMARDY[0:1]#), and IDE_IRDY[0:1]
(DSTROBE[0:1]) signal lines are no longer in effect after IDE_DREQ[0:1] and IDE_DACK[0:1] are de-asserted.

Figure 9-31. Host Terminating an UltraDMA Data In Burst Timing Diagram

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LI
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RP
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AZ
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t
LI
RFS
t
MLI
t
t
ACK
ZAH
t
ACK
t
MLI
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IORDYZ
t t
DVS DVH
CR
t
ACK
AMD Geode™ SC3200 Processor Data Book
Electrical Specifications