AMD Geode SC3200 Data Book page 63

Signal Definitions
3.4.14 AC97 Audio Interface Signals
Signal Name Ball No.
BIT_CLK U30
SDATA_OUT P29
SDATA_IN U31
SDATA_IN2 AL8
SYNC P30
AC97_CLK P31
AC97_RST# U29
PC_BEEP V31
AMD Geode™ SC3200 Processor Data Book
Type Description
I Audio Bit Clock. The serial bit clock from the codec.
Note: If selected as BIT_CLK function but not used, tie
BIT_CLK low.
O Serial Data Output. This output transmits audio serial
data to the codec.
I Serial Data Input. This input receives serial data from
the primary codec.
Note: If selected as SDATA_IN function but not used,
tie SDATA_IN low.
I Serial Data Input 2. This input receives serial data from
the secondary codec. This signal has wakeup capability.
O Serial Bus Synchronization. This bit is asserted to syn-
chronize the transfer of data between the SC3200 and
the AC97 codec.
O Codec Clock. It is twice the frequency of the Audio Bit
Clock.
O Codec Reset. S3 to S5 wakeup is not supported
because AC97_RST# is powered by V
states S3 to S5 are needed, a circuit in the system board
should be used to reset the AC97 codec.
O PC Beep. Legacy PC/AT speaker output.
32581C
F_TRDY#
TFT_PRSNT (Strap)
F_GNT0#
CLKSEL3 (Strap)
F_STOP#
. If wakeup from
IO
GPIO16+
F_DEVSEL#
Mux
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