Table 9-21. Sub-Isa Timing Parameters - AMD Geode SC3200 Data Book

Electrical Specifications
9.3.6 Sub-ISA Interface
All output timing is guaranteed for 50 pF load, unless other-
wise specified.
Symbol Parameter
t MEMR#/DOCR#/RD#/TRDE# read
RD1
active pulse width FE to RE
t MEMR#/DOCR#/RD#/TRDE# read
RD2
active pulse width FE to RE
t IOR#/RD#/TRDE# read active pulse
RD3
width FE to RE
t IOR#/MEMR#/DOCR#/RD#/TRDE#
RD4
read active pulse width FE to RE
t IOR#/MEMR#/DOCR#/RD#/TRDE#
RD5
read active pulse width FE to RE
t MEMR#/DOCR#/RD#/TRDE#
RCU1
inactive pulse width
t MEMR#/DOCR#/RD#/TRDE#
RCU2
inactive pulse width
t IOR#/RD#/TRDE# inactive pulse
RCU3
width
t MEMW#/WR# write active pulse
WR1
width FE to RE
t MEMW#/DOCW#/WR# write active
WR2
pulse width FE to RE
t IOW#/WR# write active pulse width
WR3
FE to RE
t IOW#/MEMW#/DOCW#/WR# write
WR4
active pulse width FE to RE
t IOW#/MEMW#/DOCW#/WR# write
WR5
active pulse width FE to RE
t MEMW#/WR#/DOCW# inactive pulse
WCU1
width
t MEMW#/WR#/DOCW# inactive pulse
WCU2
width
t IOW#/WR# inactive pulse width
WCU3
t IOR#/MEMR#/RD#/DOCR#/IOW#/
RDYH
MEMW#/WR#/DOCW# hold after
IOCHRDY RE
t IOCHRDY valid after IOR#/MEMR#/
RDYA1
RD#/DOCR#/IOW#/MEMW#/WR#/
DOCW# FE
AMD Geode™ SC3200 Processor Data Book
The ISA Clock divisor (defined in F0 Index 50h[2:0] of the
Core Logic module) is 011.

Table 9-21. Sub-ISA Timing Parameters

Bus
Width
(Bits) Type
16
16
16
8 M, I/O
8 M, I/O
16
8
8, 16
16
16
16
8 M, I/O
8 M, I/O
16
8
8, 16
8, 16 M, I/O
16 M, I/O
32581C
Min Max
(ns) (ns)
M 225
M 105
I/O 160
520
160
M 103
M 163
I/O 163
M 225
M 105
I/O 160
520
160
M 103
M 163
I/O 163
120
78
Figure Comments
9-19 Standard
9-19 Zero wait state
9-19 Standard
9-19 Standard
9-19 Zero wait state
9-19
9-19
9-19
9-20 Standard
9-20 Zero wait state
9-20 Standard
9-20 Standard
9-20 Zero wait state
9-20
9-20
9-20
9-19
9-20
9-19
9-20
377