Clock Generators And Plls; Figure 4-2. Clock Generation Block Diagram - AMD Geode SC3200 Data Book

General Configuration Block
4.5

Clock Generators and PLLs

This section describes the registers for the clocks required
by the GX1 module, Core Logic module, and the Video
Processor, and how these clocks are generated. See Fig-
ure 4-2 for a clock generation diagram.
32.768 KHz
Crystal
Oscillator
27 MHz
Crystal
Oscillator
Note: V powers PLL2 and PLL5. V
PLL2
AMD Geode™ SC3200 Processor Data Book
32.768 KHz
PLL4
48 MHz
Shutdown
PLL3
24.576 MHz
Shutdown
PLL6
57.273 MHz
Shutdown
Shutdown
CLK
PLL2
Shutdown
25-135 MHz
DISABLE
PLL5
66.67 MHz
Shutdown
(ACPI)
Divide
by 2
ADL
100-333 MHz
Shutdown
(ACPI)
Divider
powers PLL3, PLL4, and PLL6.
PLL3

Figure 4-2. Clock Generation Block Diagram

The clock generators are based on 32.768 KHz and 27.000
MHz crystal oscillators. The 32.768 KHz crystal oscillator is
described in Section 5.5.2 "RTC Clock Generation" on
page 103 (functional description of the RTC).
Real-Time Clock (RTC)
USB Clock (48 MHz)
and I/O Block Clock
(24.576 MHz)
High-Resolution Timer Clock
ACPI Clock (14.318 MHz)
Divide
by 4
48 MHz
Internal Fast-PCI Clock
66 MHz
33 MHz
32581C
DISABLE
AC97_CLK
To PAD
CLK27M Ball
Dot Clock
External PCI Clock
(33.3 MHz)
DISABLE
Core Clock
SDRAM Clock
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