Table 4-6. Core Clock Frequency; Table 4-7. Strapped Core Clock Frequency - AMD Geode SC3200 Data Book

General Configuration Block
4.5.2 GX1 Module Core Clock
The core clock is generated by an Analog Delay Loop
(ADL) clock generator from the internal Fast-PCI clock. The
clock can be any whole-number multiple of the input clock
between 4 and 10. Possible values are listed in Table 4-6.
At power-on reset, the core clock multiplier value is set
according to the value of four strapped balls - CLKSEL[3:0]
(balls P30, D29, AF3, B8). These balls also select the clock
which is used as input to the multiplier, as shown in Table
4-7.
4.5.3 Internal Fast-PCI Clock
The internal Fast-PCI clock can be configured to 33, 48, or
66 MHz via strap options on the CLKSEL1 and CLKSEL0
balls. These can be read in the internal Fast-PCI Clock field
in the CCFC register (GCB+I/O Offset 1Eh[9:8]). (See
Table 4-8 on page 85 details on the CCFC register.)
Internal Fast-PCI Clock
CLKSEL[3:0] Freq. (MHz)
Straps (GCB+I/O Offset 1Eh[9:8])
0111
1011
1111
0000
0100
1000
1100
0001
0101
1001
1101
0110
1010
Note: Not all speeds are supported. For information on supported speeds, see Section A.1 "Order Information" on page
425.
AMD Geode™ SC3200 Processor Data Book

Table 4-7. Strapped Core Clock Frequency

Multiply By
33.33 4
5
6
7
8
9
10
48 4
5
6
7
66.67 4
5

Table 4-6. Core Clock Frequency

ADL Internal Fast-PCI Clock Freq. (MHz)
Multiplier
Value 33.33
4 133.3
5 166.7
6 200
7 233.3
8 266.7
9 ---
10 ---
Default ADL Multiplier
Multiplier Value
(GCB+I/O Offset 1Eh[3:0])
0100
0101
0110
0111
1000
1001
1010
0100
0101
0110
0111
0100
0101
32581C
48 66.67
192 266.7
240 ---
288 ---
--- ---
--- ---
--- ---
--- ---
Maximum Core
Clock Freq. (MHz)
133
167
200
233
266
Reserved
Reserved
192
240
288
Reserved
266
Reserved
83