Figure 9-4. Memory Controller Output Valid Timing Diagram; Figure 9-5. Read Data In Setup And Hold Timing Diagram - AMD Geode SC3200 Data Book

Electrical Specifications
SDCLK[3:0]
Control Output, MA[12:0]
BA[1:0], MD[63:0]

Figure 9-4. Memory Controller Output Valid Timing Diagram

V
REF
SDCLK_IN
MD[63:0]
Read Data In
AMD Geode™ SC3200 Processor Data Book
t , t
1
V
REF
t t
4 5
Data Valid

Figure 9-5. Read Data In Setup and Hold Timing Diagram

t
6
, t
2 3
t
11
V
REF
t
4
Data Valid
32581C
t
10
t t
7 7
t
9
t
5
V
OHD
V
OLD
V
IHD
V
ILD
t
9
365