AMD Geode SC3200 Data Book page 300

32581C
Bit Description
I/O Port 0DEh
Note: Channels 5, 6, and 7 are not supported.
Bit Description
I/O Port 081h
Address bits [23:16] (byte 2).
I/O Port 082h
Address bits [23:16] (byte 2).
I/O Port 083h
Address bits [23:16] (byte 2).
I/O Port 087h
Address bits [23:16] (byte 2).
I/O Port 089h
Nor supported.
I/O Port 08Ah
Not supported.
I/O Port 08Bh
Not supported.
I/O Port 08Fh
Refresh address.
I/O Port 481h
Address bits [31:24] (byte 3).
Note: This register is reset to 00h on any access to Port 081h.
I/O Port 482h
Address bits [31:24] (byte 3).
Note: This register is reset to 00h on any access to Port 082h.
I/O Port 483h
Address bits [31:24] (byte 3).
Note: This register is reset to 00h on any access to Port 083h.
I/O Port 487h
Address bits [31:24] (byte 3).
Note: This register is reset to 00h on any access to Port 087h.
I/O Port 489h
Not supported
I/O Port 48Ah
Not spported
I/O Port 48Bh
Not supported
300
Table 6-43. DMA Channel Control Registers (Continued)
DMA Write Mask Register Command, Channels 7:4 (W)
Table 6-44. DMA Page Registers
DMA Channel 2 Low Page Register (R/W)
DMA Channel 3 Low Page Register (R/W)
DMA Channel 1 Low Page Register (R/W)
DMA Channel 0 Low Page Register (R/W)
DMA Channel 6 Low Page Register (R/W)
DMA Channel 7 Low Page Register (R/W)
DMA Channel 5 Low Page Register (R/W)
ISA Refresh Low Page Register (R/W)
DMA Channel 2 High Page Register (R/W)
DMA Channel 3 High Page Register (R/W)
DMA Channel 1 High Page Register (R/W)
DMA Channel 0 High Page Register (R/W)
DMA Channel 6 High Page Register (R/W)
DMA Channel 7 High Page Register (R/W)
DMA Channel 5 High Page Register (R/W)
Core Logic Module - ISA Legacy Register Space
AMD Geode™ SC3200 Processor Data Book