Table 5-8. Relevant Swc Registers - AMD Geode SC3200 Data Book

32581C
5.4.2.2 LDN 01h - System Wakeup Control
Table 5-8 lists registers that are relevant to the configura-
tion of System Wakeup Control (SWC). These registers are
Index Type Configuration Register or Action
30h R/W
Activate. When bit 0 is cleared, the registers of this logical device are not accessible.
60h R/W Base Address MSB register.
61h R/W Base Address LSB register. Bits [3:0] (for A[3:0]) are RO, 0000b.
70h R/W Interrupt Number. (For routing the internal PWUREQ signal.)
71h R/W Interrupt Type. Bit 1 is R/W. Other bits are RO.
74h RO Report no DMA assignment.
75h RO Report no DMA assignment.
1. The logical device registers are maintained, and all wakeup detection mechanisms are functional.
98
described earlier in Table 5-3 "Standard Configuration Reg-
isters" on page 93.

Table 5-8. Relevant SWC Registers

SuperI/O Module
AMD Geode™ SC3200 Processor Data Book
Reset
Value
1 00h
00h
00h
00h
03h
04h
04h