Figure 2-2 Host Interface Block Diagram - AMD 780E Technical Reference Manual

HyperTransport I/O Link Specification from the HyperTransport Consortium.
Diagram," illustrates the basic blocks of the host bus interface of the RS780E.
The HyperTransport (HT) Interface, formerly known as the LDT (Lightning Data Transport) interface, is a high speed,
packet-based link implemented on two unidirectional buses. It is a point-to-point interface where data can flow both
upstream and downstream at the same time. The commands, addresses, and data travel in packets on the HyperTransport
link. Lengths of packets are in multiples of four bytes. The HT link consists of three parts: the physical layer (PHY), the
data link layer, and the protocol/transaction layer. The PHY is the physical interface between the RS780E and the CPU.
The data link layer includes the initialization and configuration sequences, periodic redundancy checks,
connect/disconnect sequences, and information packet flow controls. The protocol layer is responsible for maintaining
strict ordering rules defined by the HT protocol.
The RS780E HyperTransport bus interface consists of eighteen unidirectional differential data/control pairs and two
differential clock pairs in each of the upstream and downstream direction. On power up, the HT link is 8-bit wide and runs
at a default speed of 400MT/s. After negotiation, carried out by the HW and SW together, the link width can be brought
up to 16-bit and the interface can run up to 4.4GT/s. The interface is illustrated in
Interface Signals."
signal names may be different from those used in the pin listing of the RS780E. Detailed descriptions of the signals are
given in section 3.3, "CPU HyperTransport™ Interface‚' on page
45732 AMD 780E Databook 3.10
2-2
HT Interface to CPU (PHY)
Configuration
Registers
Root Complex

Figure 2-2 Host Interface Block Diagram

The signal name and direction for each signal is shown with respect to the processor. Note that the
LTA
LRA
Protocol/Transaction Layer
SCH
Memory Controller
3-5.
Figure 2-2, "Host Interface Block
Data Link Layer
Figure 2-3, "RS780E Host Bus
© 2009 Advanced Micro Devices, Inc.
Host Interface
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