32581C
USB
Interface
Serial Ports
(UARTs)/IDE
Interface
IR Port
Interface
AC97 Audio
Interface
Power
Management
Interface
JTAG
Interface
The remaining subsections of this chapter describe:
• Section 3.1 "Ball Assignments": Provides a ball assign-
ment diagram and tables listing the signals sorted
according to ball number and alphabetically by signal
name.
• Section 3.2 "Strap Options": Several balls are read at
power-up that set up the state of the SC3200. This
section provides details regarding those balls.
26
POWER_EN
OVER_CUR#
DPOS_PORT1
DNEG_PORT1
DPOS_PORT2
AMD Geode™
DNEG_PORT2
SC3200
DPOS_PORT3
Processor
DNEG_PORT3
SIN1
SIN2+SDTEST3
SOUT1+CLKSEL1
SOUT2+CLKSEL2
GPIO7+RTS2#+IDE_DACK1#+SDTEST0
GPIO8+CTS2#+IDE_DREQ1+SDTEST4
GPIO18+DTR1#/BOUT1
GPIO6+DTR2#/BOUT2+IDE_IOR1#+SDTEST5
GPIO11+RI2#+IRQ15
GPIO9+DCD2#+IDE_IOW1#+SDTEST2
GPIO10+DSR2#+IDE_IORDY1+SDTEST1
IRRX1+SIN3
IRTX+SOUT3
BIT_CLK
SDATA_OUT+TFT_PRSNT
SDATA_IN
SDATA_IN2
SYNC+CLKSEL3
AC97_CLK
AC97_RST#
GPIO16+PC_BEEP
CLK32
GPWIO[2:0]
LED#
ONCTL#
PWRBTN#
PWRCNT[1:2]
THRM#
TCK
TDI
TDO
TMS
TRST#
Figure 3-1.
Signal Groups (Continued)
PCICLK0+FPCI_MON
PCICLK1+LPC_ROM
PCICLK
INTA#, INTB#
FRAME#
LOCK#
PERR#
SERR#
REQ[1:0]#
GNT0#+DID0
GNT1#+DID1
A[23:0]/AD[23:0]
D[7:0]/AD[31:24]
D[11:8]/C/BE[3:0]#
D12/PAR
D13/TRDY#
D14/IRDY#
D15/STOP#
BHE#/DEVSEL#
GPIO17+TFTDCK+IOCS0#
GPIO1+IOCS1+TFTD12
ROMCS#/BOOT16
GPIO20+DOCCS#+TFTD0
RD#+CLKSEL0
WR#
GPIO14+DOCR#+IOR#
GPIO15+DOCW#+IOW#
GPIO0+TRDE#
GPIO19+INTC#+IOCHRDY
GPIO32+LAD0
GPIO33+LAD1
GPIO34+LAD2
GPIO35+LAD3
GPIO36+LDRQ#
GPIO37+LFRAME#
GPIO38+IRRX2+LPCPD
GPIO39+SERIRQ
TEST1+PLL6B
TEST0+PLL2B
GXCLK+FP_VDD_ON+TEST3
TEST2+PLL5B
GTEST
TDP, TDN
• Section 3.3 "Multiplexing Configuration": Lists multi-
plexing options and their configurations.
• Section 3.4 "Signal Descriptions": Detailed descriptions
of each signal according to functional group.
AMD Geode™ SC3200 Processor Data Book
Signal Definitions
Sub-ISA/PCI Bus
Interface
GPIO/LPC Bus
Interface
Test and
Measurement
Interface
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