Figure 9-15. Load Circuits For Maximum Time Measurements; Table 9-19. Pci Timing Parameters - AMD Geode SC3200 Data Book

32581C
Symbol Parameter
t PCICLK to signal valid delay (on the bus)
VAL
t (ptp) PCICLK to signal valid delay (GNT#)
VAL
t Float to active delay
ON
t Active to float delay
OFF
t Input setup time to PCICLK (on the bus)
SU
t (ptp) Input setup time to PCICLK (REQ#)
SU
t Input hold time from PCICLK
H
t PCIRST# active time after power stable
RST
t PCIRST# active time after PCICLK stable
RST-CLK
t PCIRST# active to output float delay
RST-OFF
Note 1. See the timing measurement conditions in Figure 9-16.
Note 2. Minimum times are evaluated with same load used for slew rate measurement (as shown in note 3 of Table ); max-
imum times are evaluated with the load circuits shown in Figure 9-15, for high-going and low-going edges respec-
tively.
Note 3. Not 100% tested.
Note 4. See the timing measurement conditions in Figure 9-17.
Note 5. PCIRST# is asserted and de-asserted asynchronously with respect to PCICLK (see Figure 9-18).
Note 6. All output drivers are asynchronously floated when PCIRST# is active.
t (Max) Rising Edge
VAL
0.5" max.
Pin
Output
Buffer
Ω
25

Figure 9-15. Load Circuits for Maximum Time Measurements

374

Table 9-19. PCI Timing Parameters

10 pF
Min Max Unit
2 11
2 9
2
28
7
6
0
1
100
40
t (Max) Falling Edge
VAL
0.5" max.
Output
Buffer
10 pF
AMD Geode™ SC3200 Processor Data Book
Electrical Specifications
Comments
ns Note 1, Note 2
ns Note 1, Note 2
ns Note 1, Note 3,
ns Note 1, Note 3,
ns Note 4
ns Note 4
ns Note 4
ms Note 3, Note 5
µs Note 3, Note 5
ns Note 3, Note 5,
Note 6
V
CC
Ω
25