Figure 9-49. Ac97 Clocks Diagram; Table 9-37. Ac97 Clocks Parameters - AMD Geode SC3200 Data Book

Electrical Specifications
Symbol Parameter
F BIT_CLK frequency
BIT_CLK
t BIT_CLK period
CLK_PD
t BIT_CLK output jitter
CLK_J
t BIT_CLK high pulse width
CLK_H
t BIT_CLK low pulse width
CLK_L
F SYNC frequency
SYNC
t SYNC period
SYNC_PD
t SYNC high pulse width
SYNC_H
t SYNC low pulse width
SYNC_L
F AC97_CLK frequency
AC97_CLK
t AC97_CLK period
AC97_CLK_PD
t AC97_CLK duty cycle
AC97_CLK_D
t AC97_CLK fall/rise time
AC97_CLK_FR
t AC97_CLK output edge-to-
AC97_CLK_J
edge jitter
Note 1. Worst case duty cycle restricted to 40/60.
BIT_CLK
SYNC
AC97_CLK
AMD Geode™ SC3200 Processor Data Book

Table 9-37. AC97 Clocks Parameters

Min
32.56
32.56
45
2
t
CLK_H
t
CLK_PD
t
SYNC_H
t
t
AC97_CLK_PD
V
OHD
V
OLD
t
AC97_CLK_FR

Figure 9-49. AC97 Clocks Diagram

Typ Max Unit
12.288 MHz
81.4 ns
750 ps
40.7 48.84 ns
40.7 48.84 ns
48.0 KHz
20.8 µs
1.3 µs
19.5 µs
24.576 MHz
40.7 ns
55 %
5 ns
100 ps
t
CLK_L
t
SYNC_L
SYNC_PD
32581C
Comments
Note 1
Note 1
Measured from edge to edge
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