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Signal Definitions
Table 3-2.
Ball
I/O
No.
Signal Name
(PU/PD)
5
MD44
I/O
AL20
5
MD40
I/O
AL21
AL22
CKEA
O
AL23
MA7
O
AL24
MA4
O
5
MD8
I/O
AL25
5
MD10
I/O
AL26
5
MD9
I/O
AL27
AL28
MA12
O
MD23
I/O
5
AL29
AMD Geode™ SC3200 Processor Data Book
BGU481 Ball Assignment - Sorted by Ball Number (Continued)
1
Buffer
Power
Type
Rail
Configuration
IN
,
V
---
T
IO
TS
2/5
IN
,
V
---
T
IO
TS
2/5
O
V
---
2/5
IO
O
V
---
2/5
IO
O
V
---
2/5
IO
IN
,
V
---
T
IO
TS
2/5
IN
,
V
---
T
IO
TS
2/5
IN
,
V
---
T
IO
TS
2/5
O
V
---
2/5
IO
IN
,
V
---
T
IO
TS
2/5
Ball
I/O
No.
Signal Name
(PU/PD)
AL30
V
PWR
IO
AL31
V
GND
SS
1.
For Buffer Type definitions, refer to Table 9-10 "Buffer Types" on page
357.
2.
Is 5V tolerant (ACK#, AFD#/DSTRB#, BUSY/WAIT#, ERR#, INIT#,
PD[7:0], PE, SLCT, SLIN#/ASTRB#, STB#/WRITE#, ONCTL#,
PWRCNT[2:1]).
3.
The TFT_PRSNT strap determines the power-on reset (POR) state of
PMR[23].
4.
The LPC_ROM strap determines the power-on reset (POR) state of
PMR[14] and PMR[22].
5.
Is back-drive protected (MD[63:0], DPOS_PORT1, DNEG_PORT1,
DPOS_PORT2, DNEG_PORT2, DPOS_PORT3, DNEG_PORT3,
ACK#, AFD#/DSTRB#, BUSY/WAIT#, ERR#, INIT#, PD[7:0], PE,
SLCT, SLIN#/ASTRB#, STB#/WRITE#, ONCTL#, PWRCNT[2:1]).
32581C
1
Buffer
Power
Type
Rail
Configuration
---
---
---
---
---
---
39
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