Figure 9-26. Multiword Dma Data Transfer Timing Diagram - AMD Geode SC3200 Data Book

32581C
IDE_CS[1:0]#
IDE_DREQ0
IDE_DACK0#
IDE_IOR0#
IDE_IOW0#
IDE_DATA[15:0]
IDE_DATA[15:0]
Notes:
1) For Multiword DMA transfers, the Device may negate IDE_DREQ[0:1] within the tL specified time once IDE_DACK[0:1
is asserted, and reassert it again at a later time to resume the DMA operation. Alternatively, if the device is able to co
tinue the transfer of data, the device may leave IDE_DREQ[0:1] asserted and wait for the host to reasse
IDE_DACK[0:1]#.
2) This signal can be negated by the host to Suspend the DMA transfer in process.

Figure 9-26. Multiword DMA Data Transfer Timing Diagram

388
t
M
t
t
I
D
t
E
t
t
F
G
t
t
G
H
t
0
t
L
t
K
AMD Geode™ SC3200 Processor Data Book
Electrical Specifications
t
N
t
j
t
Z