Table 9-27. Ide Ultradma Data Burst Timing Parameters - AMD Geode SC3200 Data Book

Electrical Specifications
Symbol Parameter
t Typical sustained average two cycle time
2CYC
Two cycle time allowing for clock variations
(from rising edge to next rising edge or from
falling edge to next falling edge of STROBE)
t Cycle time allowing for asymmetry and clock
CYC
variations (from STROBE edge to STROBE
edge)
t Data setup time (at recipient)
DS
t Data hold time (at recipient)
DH
t Data valid setup time at sender (from data
DVS
bus being valid until STROBE edge)
t Data valid hold time at sender (from
DVH
STROBE edge until data may become
invalid)
t First STROBE time (for device to first negate
FS
IDE_IRDY[0:1] (DSTROBE[0:1]) from
IDE_IOW[0:1]# (STOP[0:1]) during a data in
burst)
t Limited interlock time
LI
t Interlock time with minimum
MLI
t Unlimited interlock time
UI
t Maximum time allowed for output drivers to
AZ
release (from being asserted or negated)
t Minimum delay time required for output driv-
ZAH
ers to assert or negate (from released state)
t
ZAD
t Envelope time (from IDE_DACK[0:1]# to
ENV
IDE_IOW[0:1]# (STOP[0:1]) and
IDE_IOR[0:1]# (HDMARDY[0:1]#) during
data out burst initiation)
t STROBE to DMARDY time (if DMARDY# is
SR
negated before this long after STROBE
edge, the recipient receives no more than
one additional data WORD)
t Ready-to-final-STROBE time (no STROBE
RFS
edges are sent this long after negation of
DMARDY#)
t Ready-to-pause time (time that recipient
RP
waits to initiate pause after negating
DMARDY#)
t Pull-up time before allowing IDE_IORDY[0:1]
IORDYZ
to be released
t Minimum time device waits before driving
ZIORDY
IDE_IORDY[0:1]
t Setup and hold times for IDE_DACK[0:1]#
ACK
(before assertion or negation)
t Time from STROBE edge to negation of
SS
IDE_DREQ[0:1] or assertion of
IDE_IOW[0:1]# (STOP[0:1]) (when sender
terminates a burst)
Note 1. t , t , and t indicate sender-to-recipient or recipient-to-sender interlocks, that is, one agent (either sender or recipient) is wait-
UI MLI LI
ing for the other agent to respond with a signal before proceeding. t
is a limited timeout with a defined minimum. t
AMD Geode™ SC3200 Processor Data Book

Table 9-27. IDE UltraDMA Data Burst Timing Parameters

is a limited time-out with a defined maximum.
LI
Mode 0 Mode 1
Min Max Min Max
240 160
235 156
114 75
15 10
5 5
70 48
6 6
0 230 0 200
0 150 0 150
20 20
0 0
10 10
20 20
0 0
20 70 20 70
50 30
75 60
160 125
20 20
0 0
20 20
50 50
is an unlimited interlock with no maximum time value. t
UI
32581C
Mode 2
Min Max Unit Comments
120 ns
117 ns
55 ns
7 ns
5 ns
34 ns
6 ns
0 170 ns
0 150 ns Note 1
20 ns Note 1
0 ns Note 1
10 ns
20 ns
0 ns
20 70 ns
20 ns
50 ns
100 ns
20 ns
0 ns
20 ns
50 ns
MLI
389