32581C
3.4.4
TFT Interface Signals
Signal Name
Ball No.
HSYNC
A11
VSYNC
B11
TFTDCK
AA1
A10
TFTDE
P2
B18
FP_VDD_ON
AB1
V30
TFTD[17:0]
See
Table 3-3
on page
40.
3.4.5
ACCESS.bus Interface Signals
Signal Name
Ball No.
AB1C
N31
AB1D
N30
AB2C
N29
AB2D
M29
52
Type
Description
O
Horizontal Sync
O
Vertical Sync
O
TFT Clock.
O
TFT Data Enable.
O
TFT Power Control. Used to enable power to the flat
panel display, with power sequence timing.
O
Digital RGB Data to TFT.
TFTD[5:0] - Connect to the BLUE TFT inputs.
TFTD[11:6] - Connect to GREEN TFT inputs.
TFTD[17:12] - Connect to RED TFT inputs.
Type
Description
I/O
ACCESS.bus 1 Serial Clock. This is the serial clock for
the interface.
Note:
If selected as AB1C function but not used, tie
AB1C high.
I/O
ACCESS.bus 1 Serial Data. This is the bidirectional
serial data signal for the interface.
Note:
If AB1D function is selected but not used, tie
AB1D high.
I/O
ACCESS.bus 2 Serial Clock. This is the serial clock for
the interface.
Note:
If AB2C function is selected but not used, tie
AB2C high.
I/O
ACCESS.bus 2 Serial Data. This is the bidirectional
serial data signal for the interface.
Note:
If AB2D function is selected but not used, tie
AB2D high.
Signal Definitions
IDE_RST#
GPIO17+ IOCS0#
IDE_CS1#
ACK#+FPCICLK
IDE_DATA4
GXCLK+TEST3
The TFT interface is
muxed with the IDE
interface or the Par-
allel Port. See Table
3-5 on page 45 and
Table 3-6 on page
46 for details.
GPIO20+DOCCS#
GPIO1+IOCS1#
AMD Geode™ SC3200 Processor Data Book
Mux
---
---
Mux
GPIO12
GPIO13
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