Block Diagram; Related Xilinx Documents - Xilinx SP601 User Manual

Block Diagram

Figure 1-1
X-Ref Target - Figure 1-1
DIP Switch
GPIO Header
USB
JTAG Connector
DDR2
Pushbuttons
IIC EEPROM
and Header

Related Xilinx Documents

Prior to using the SP601 Evaluation Board, users should be familiar with Xilinx resources.
See the following locations for additional documentation on Xilinx tools and solutions:
•
•
•
SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
shows a high-level block diagram of the SP601 and its peripherals.
LEDs
Expansion Connector
DED
Spartan-6
Bank 3
XC6SLX16
1.8V
MODE
DIP Switch
Figure 1-1: SP601 Features and Banking
ISE: www.xilinx.com/ise
Answer Browser: www.xilinx.com/support
Intellectual Property: www.xilinx.com/ipcenter
www.xilinx.com
FMC LPC
Bank 0
2.5 V
Bank 1
2.5V
U1
Bank 2
2.5V
SPI x4 or
External Config
Related Xilinx Documents
10/100/1000
Ethernet GMII
Parallel Flash
Differential Clock
Clock Socket
SMA Clock
USB UART
UG518_01_070809
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