Xilinx Spartan-6 FPGA User Manual
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Xilinx Spartan-6 FPGA User Manual

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Spartan-6 FPGA
Power Management
User Guide
UG394 (v1.1) September 4, 2012

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Summary of Contents for Xilinx Spartan-6 FPGA

  • Page 1 Spartan-6 FPGA Power Management User Guide UG394 (v1.1) September 4, 2012...

  • Page 2: Revision History

    (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same.

  • Page 3: Table Of Contents

    Synchronizing Wake-Up ........... 22 Spartan-6 FPGA Power Management www.xilinx.com...
  • Page 4 ........39 www.xilinx.com Spartan-6 FPGA Power Management UG394 (v1.1) September 4, 2012...

  • Page 5: Preface: About This Guide

    • Spartan-6 Family Overview This overview outlines the features and product selection of the Spartan-6 family. • Spartan-6 FPGA Data Sheet: DC and Switching Characteristics This data sheet contains the DC and switching characteristic specifications for the Spartan-6 family. •...

  • Page 6: Additional Support Resources

    Spartan-6 FPGAs offer lower power, simpler power systems and PCB complexity, better reliability, and lower system cost. This white paper details how Xilinx designed for this new reality in Spartan-6 (45 nm) and Virtex®-6 (40 nm) FPGA families, achieving dramatic power reductions over previous generation devices.

  • Page 7: Chapter 1: Power Management With Suspend Mode

    FPGA to return to the normal application. Suspend Synchronization The Spartan-6 FPGA primitive, SUSPEND_SYNC, enables the synchronization of the suspend action with the application design. In the Extended Spartan-3A family, the suspend mode activation begins immediately upon asserting the SUSPEND pin. The...

  • Page 8: Suspend Features

    AWAKE Pin Behavior when Suspend Feature is Enabled, page 21 Entering Suspend Mode Figure 1-1 is a block diagram of the FPGA entering suspend mode. Figure 1-2, page 10 shows example waveforms. www.xilinx.com Spartan-6 FPGA Power Management UG394 (v1.1) September 4, 2012...
  • Page 9 FPGA inputs and interconnects are shut down. This allows the design state to be held static during suspend mode. If a specific design state must be maintained, see Design Requirements to Maintain Application Data, page Spartan-6 FPGA Power Management www.xilinx.com UG394 (v1.1) September 4, 2012...
  • Page 10 The states of all flip-flops, block RAM, distributed RAM (LUT RAM), shift registers (SRL), and I/O latches are preserved during suspend mode. www.xilinx.com Spartan-6 FPGA Power Management UG394 (v1.1) September 4, 2012...
  • Page 11 RAM), shift registers (SRL), and I/O latches. By default, the clocked primitives are released five clock cycles after AWAKE transitions High. The write-protect lock should be held until after outputs are enabled. Spartan-6 FPGA Power Management www.xilinx.com UG394 (v1.1) September 4, 2012...

  • Page 12: Exiting Suspend Mode

    FPGA outputs are re-enabled and when the write-protect lock is released from all writable clocked primitives. These timers begin after the AWAKE pin is High. The wake-up timing clock source is also programmable. www.xilinx.com Spartan-6 FPGA Power Management UG394 (v1.1) September 4, 2012...
  • Page 13 Glitch Filter Suspend Enable drive_awake ENABLE_SUSPEND Filter Select ENABLE_SUSPEND SCP0 edge detector wakeup_mask<0> SCP1 edge detector Multi-Pin Wake-up wakeup_mask<1> multipin_wakeup SCP7 edge detector wakeup_mask<7> UG394_c1_03_020310 Figure 1-3: Exiting Suspend Mode Spartan-6 FPGA Power Management www.xilinx.com UG394 (v1.1) September 4, 2012...

  • Page 14: Program_B Programming Pin Always Overrides Suspend Mode

    However, this method is not recommended because it does not automatically reserve the AWAKE pin in the application. bitgen -g en_suspend:Yes The following option enables the glitch filter on the SUSPEND pin. bitgen -g suspend_filter:Yes www.xilinx.com Spartan-6 FPGA Power Management UG394 (v1.1) September 4, 2012...

  • Page 15: Define The Multi-Pin Wake-Up Feature And Pins

    The DRIVE_LAST_VALUE attribute is not supported for differential output drivers. Treat the pseudo-differential I/O standards, such as BLVDS, DIFF_HSTL, and DIFF_SSTL, as two single-ended I/O pins. All the attributes apply as for Single-Ended I/O Standards Spartan-6 FPGA Power Management www.xilinx.com UG394 (v1.1) September 4, 2012...

  • Page 16: Suspend Attribute

    FPGA awakens from suspend mode. By default, en_sw_gsr:No signifies that clocked primitives are not set or reset when the FPGA awakens and all states are preserved. www.xilinx.com Spartan-6 FPGA Power Management UG394 (v1.1) September 4, 2012...

  • Page 17: Design Requirements To Maintain Application Data

    Table 1-3. The clock source is defined by one or two bitstream generator options, sw_clk and sometimes StartupClk. The internal oscillator is disabled during suspend mode to conserve power. Spartan-6 FPGA Power Management www.xilinx.com UG394 (v1.1) September 4, 2012...
  • Page 18 CLK input on the originate from any non-clocked signal in the FPGA. It UserClk STARTUP_SPARTAN6 cannot originate from a flip-flop source because all design primitive clocked primitives are write-protected while in suspend mode. www.xilinx.com Spartan-6 FPGA Power Management UG394 (v1.1) September 4, 2012...

  • Page 19: Switch Outputs From Suspend To Normal Behavior

    JTAG Operations Allowed During Suspend Mode Table 1-4 shows the JTAG operations permitted when the FPGA is in suspend mode. Executing these JTAG operations increases the FPGA's power consumption while in suspend mode. Spartan-6 FPGA Power Management www.xilinx.com UG394 (v1.1) September 4, 2012...

  • Page 20: Suspend Pin

    Table 1-4: JTAG Operations Allowed during Suspend Mode Boundary-Scan Description Command Read the JTAG ID code that describes the Spartan-6 FPGA array IDCODE type in the JTAG chain. This value is different from the Device DNA identifier, which is unique to every device.

  • Page 21: Suspend Input Glitch Filter

    The AWAKE pin can further be configured as an open-drain output (the default) or a full-swing output driver, as shown in Figure 1-5. This behavior is controlled by a bitstream generator (BitGen) option: bitgen -g drive_awake:no Spartan-6 FPGA Power Management www.xilinx.com UG394 (v1.1) September 4, 2012...

  • Page 22: Controlling Wake-Up From An External Source

    If an active application uses the post-configuration CRC feature and an error occurs, do not enter suspend mode. If there is a CRC error, the FPGA does not wake from suspend mode without reprogramming, such as asserting PROGRAM_B or power-cycling the FPGA. www.xilinx.com Spartan-6 FPGA Power Management UG394 (v1.1) September 4, 2012...
  • Page 23 AWAKE pin goes High. Generally, this value is equal to or less than the sw_gwe_cycle setting. multipin_wakeup Disables multi-pin wake-up. (Default) Enables multi-pin wake-up. wakeup_mask Masks out SCP<7:0> 0x00 (Default) <hex string> FF enables SCP<7:0>, 0F enables SCP<3:0>. Spartan-6 FPGA Power Management www.xilinx.com UG394 (v1.1) September 4, 2012...

  • Page 24: Fpga Voltage Requirements During Suspend Mode

    CCAUX restarts configuration. Memory Controller Block Recommendations and methods for using the memory controller block interface with the Spartan-6 FPGA suspend mode are found in UG388, Spartan-6 FPGA Memory Controller Block User Guide. www.xilinx.com Spartan-6 FPGA Power Management UG394 (v1.1) September 4, 2012...
  • Page 25 HSTL/SSTL standards. The GTP transceivers have dedicated analog power rails (see UG386, Spartan-6 FPGA GTP Transceivers User Guide for more details). The AES circuitry has its own power supplies for the encryption key, depending on how it is stored (see UG380, Spartan-6 FPGA Configuration User Guide for more details).

  • Page 26: Chapter 2: Voltage Supplies

    2.5V. If V is 2.5V or 3.3V, CCO_2 CCAUX CCO_2 can be either 2.5V or 3.3V. See UG380, Spartan-6 FPGA Configuration User Guide. CCAUX The -1L speed grade devices require V = 2.5V when using the LVDS_25, LVDS_33, CCAUX BLVDS_25, LVPECL_25, RSDS_25, RSDS_33, PPDS_25, and PPDS_33 I/O standards on inputs.

  • Page 27: Setting The Vccaux Level

    3.45V). The data retention voltage is the same for both at 2.0V, so more care must be taken with a 2.5V rail to not let it drop more than 0.5V. See DS162, Spartan-6 FPGA Data Sheet: DC and Switching Characteristics for complete specifications.

  • Page 28: Vref

    As a result, an isolated reference supply is usually a more robust and simpler approach. Refer to UG381, Spartan-6 FPGA SelectIO Resources User Guide for more details on V Board Design and Signal Integrity Building a working system today requires knowledge of the many options available.

  • Page 29: Chapter 3: Lower-Power Spartan-6 Lx Devices

    Design Suite in the Project Navigator. Different from the ordering code or actual device marking, the Xilinx tools display the part number with an appended L (for example, XC6SLX16L). The only speed grade supported for these devices is the -1L. The same speed grade supports both the commercial and industrial temperature ranges.

  • Page 30: Lower-Power Spartan-6 Lx Device Specifications

    Lower-Power Spartan-6 LX Device Specifications Several specifications are different for the lower-power Spartan-6 LX devices than in the standard Spartan-6 LX family. All of the differences are listed in DS162, Spartan-6 FPGA Data Sheet: DC and Switching Characteristics. The lower-power Spartan-6 LX devices require a V of 1.0V ±5%, or 0.95V to 1.05V.

  • Page 31: Chapter 4: Power-On And Power-Down Behavior Including Hibernate

    POR reset is released and the FPGA begins its configuration process. X-Ref Target - Figure 4-1 Spartan-6 FPGA Power-On CCINT Reset Glitch Reset CCAUX Filter Configuration Logic CCO_2 Glitch PROGRAM_B Filter UG394_c4_01_022210 Figure 4-1: Simplified POR Circuit Diagram Spartan-6 FPGA Power Management www.xilinx.com UG394 (v1.1) September 4, 2012...

  • Page 32: Supply Sequencing

    Power-Up in UG380, Spartan-6 FPGA Configuration User Guide. Supply Sequencing The Spartan-6 FPGA can be powered up and powered down in any sequence. Because the three FPGA supply inputs must be valid to release the POR and can be supplied in any order, there is no FPGA-specific voltage sequencing requirement.

  • Page 33: Configuration Data Retention And Brown Out

    The FPGA's configuration data is stored in robust CMOS configuration latches. The data in these latches is retained even when the voltages drop to the minimum levels necessary to preserve RAM contents, as specified in DS162, Spartan-6 FPGA Data Sheet: DC and Switching Characteristics (V...

  • Page 34: Forcing Fpga To Quiescent Current Levels

    FPGA PROGRAM_B UG394_c4_02_111109 Figure 4-2: Spartan-6 FPGA Power-Off Diagram Forcing FPGA to Quiescent Current Levels Before removing the power supplies, it is recommended to first put the device into the quiescent state. Pulse PROGRAM_B Low to achieve the quiescent current levels. Driving PROGRAM_B Low forces all I/Os into a high-impedance state, ceases all internal switching, and converts the bitstream held in internal memory to all zeros.

  • Page 35: Turn Off Vcco

    Turn Off V Spartan-6 FPGA I/O pins have a floating-well structure, providing full hot-swap/ hot-insertion capability. When a Spartan-6 FPGA is in the Hibernate state, the V supply can be safely turned off without adversely affecting either the FPGA or the external application.

  • Page 36: Exiting Hibernate

    FPGA configuration when power is re-applied. For specific information on configuration pins and their associated power rails, refer to UG380, Spartan-6 FPGA Configuration User Guide. www.xilinx.com Spartan-6 FPGA Power Management...

  • Page 37: Chapter 5: Power Estimation

    Chapter 5 Power Estimation Introduction Xilinx provides a complete power estimation solution using power estimators and analyzers, power-driven implementation tool algorithms, and a variety of power-related documentation. The Power Advantage page provides access to these tools, documentation, and news: http://www.xilinx.com/products/technology/power/index.htm...

  • Page 38: Saving Power

    45 nm Spartan-6 devices. Comparing Spartan-6 FPGAs to Spartan-3A FPGAs, the average static power in Spartan-6 devices is lower. Quiescent current levels are specified in DS162, Spartan-6 FPGA Data Sheet: DC and Switching Characteristics. The lower-power Spartan-6 LX devices offer the lowest quiescent current.

  • Page 39: Saving Clock Routing Power

    Minimizing the amount of routing a clock net uses is helpful, since the Xilinx software automatically disables clock nets where possible for unused areas of CLBs.
  • Page 40 Chapter 5: Power Estimation www.xilinx.com Spartan-6 FPGA Power Management UG394 (v1.1) September 4, 2012...

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