Xilinx SP601 User Manual page 19

X-Ref Target - Figure 1-7
Table 1-6: SPI x4 Memory Connections
SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
U17
DIN,DOUT,CCLK
SPI X4
FLASH
MEMORY
SPIX4_CS_B
WINBOND
W25Q64VSFIG
ON = SPI X4 U17
OFF = SPI EXT. J12
Figure 1-7: SPI Flash Interface Topology
FPGA U1
Schematic Netname
Pin
V2 FPGA_PROG_B
V14 FPGA_D2_MISO3
T14 FPGA_D1_MISO2_R
V3 SPI_CS_B
T13 FPGA_MOSI_CSI_B_MISO0
R13 FPGA_D0_DIN_MISO_MISO1
R15 FPGA_CCLK
J15.2 SPIX4_CS_B
www.xilinx.com
U1
FPGA SPI INTERFACE
SPI_CS_B
2 1
J15
SPI SELECT
JUMPER
SPI MEM U17
Pin # Pin Name
1 IO3_HOLD_B
9 IO2_WP_B
15 DIN
8 IO1_DOUT
16 CLK
7 CS_B
Detailed Description
J12
SPI PROGRAM
HEADER
UG518_07_070809
SPI HDR J12
Pin # Pin Name
1
2
3
4 TMS
5 TDI
6 TDO
7 TCK
8 GND
9 VCC3V3
19