Xilinx SP601 User Manual page 54

Appendix D: SP601 Master UCF
54
NET "FPGA_CMP_MOSI"
NET "FPGA_D0_DIN_MISO_MISO1"
NET "FPGA_D1_MISO2"
NET "FPGA_D2_MISO3"
NET "FPGA_DONE"
NET "FPGA_HSWAPEN"
NET "FPGA_INIT_B"
NET "FPGA_M0_CMP_MISO"
NET "FPGA_M1"
NET "FPGA_MOSI_CSI_B_MISO0"
NET "FPGA_ONCHIP_TERM1"
NET "FPGA_ONCHIP_TERM2"
NET "FPGA_PROG_B"
NET "FPGA_SUSPEND"
NET "FPGA_TCK_BUF"
NET "FPGA_TDI_BUF"
NET "FPGA_TDO"
NET "FPGA_TMS_BUF"
NET "FPGA_VTEMP"
NET "GPIO_BUTTON0"
NET "GPIO_BUTTON1"
NET "GPIO_BUTTON2"
NET "GPIO_BUTTON3"
NET "GPIO_HDR0"
NET "GPIO_HDR1"
NET "GPIO_HDR2"
NET "GPIO_HDR3"
NET "GPIO_HDR4"
NET "GPIO_HDR5"
NET "GPIO_HDR6"
NET "GPIO_HDR7"
NET "GPIO_LED_0"
NET "GPIO_LED_1"
NET "GPIO_LED_2"
NET "GPIO_LED_3"
NET "GPIO_SWITCH_0"
NET "GPIO_SWITCH_1"
NET "GPIO_SWITCH_2"
NET "GPIO_SWITCH_3"
NET "IIC_SCL_MAIN"
NET "IIC_SDA_MAIN"
NET "PHY_COL"
NET "PHY_CRS"
NET "PHY_INT"
NET "PHY_MDC"
NET "PHY_MDIO"
NET "PHY_RESET"
NET "PHY_RXCLK"
NET "PHY_RXCTL_RXDV"
NET "PHY_RXD0"
NET "PHY_RXD1"
NET "PHY_RXD2"
NET "PHY_RXD3"
NET "PHY_RXD4"
NET "PHY_RXD5"
NET "PHY_RXD6"
NET "PHY_RXD7"
NET "PHY_RXER"
NET "PHY_TXCLK"
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LOC = "V16";
LOC = "R13";
LOC = "T14";
LOC = "V14";
LOC = "V17";
LOC = "D4";
LOC = "U3";
LOC = "T15";
LOC = "N12";
LOC = "T13";
LOC = "L6";
LOC = "C2";
LOC = "V2";
LOC = "R16";
LOC = "A17";
LOC = "D15";
LOC = "D16";
LOC = "B18";
LOC = "P3";
LOC = "P4";
LOC = "F6";
LOC = "E4";
LOC = "F5";
LOC = "N17";
LOC = "M18";
LOC = "A3";
LOC = "L15";
LOC = "F15";
LOC = "B4";
LOC = "F13";
LOC = "P12";
LOC = "E13";
LOC = "C14";
LOC = "C4";
LOC = "A4";
LOC = "D14";
LOC = "E12";
LOC = "F12";
LOC = "V13";
LOC = "P11";
LOC = "N10";
LOC = "L14";
LOC = "M13";
LOC = "J13";
LOC = "N14";
LOC = "P16";
LOC = "L13";
LOC = "L16";
LOC = "N18";
LOC = "M14";
LOC = "U18";
LOC = "U17";
LOC = "T18";
LOC = "T17";
LOC = "N16";
LOC = "N15";
LOC = "P18";
LOC = "P17";
LOC = "B9";
SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009