Spartan-6 Xc6Slx16-2Csg324 Fpga; Configuration; I/O Voltage Rails - Xilinx SP601 User Manual

Table 1-1: SP601 Features (Cont'd)
Number

1. Spartan-6 XC6SLX16-2CSG324 FPGA

A Xilinx Spartan-6 XC6SLX16-2CSG324 FPGA is installed on the Embedded Development
Board.

Configuration

The SP601 supports configuration in the following modes:
•
•
•
•
For details on configuring the FPGA, see

I/O Voltage Rails

There are four available banks on the LX16-CS324 device. Banks 0, 1, and 2 are connected
for 2.5V I/O. Bank 3 is used for the 1.8V DDR2 component memory interface of Spartan-6
FPGA's hard memory controller. The voltage applied to the FPGA I/O banks used by the
SP601 board is summarized in
Table 1-2: I/O Voltage Rail of FPGA Banks
SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
Feature
9 VITA 57.1 FMC-LPC
connector
10 LEDs
11 LED, Header
12 LEDs
LED
DIP Switch
13
Pushbutton
12-pin (8 I/O) Header
14 Pushbutton
15 USB JTAG
16 Onboard Power
Master SPI x4
Master SPI x4 with off-board device
BPI
JTAG (using the included USB-A to Mini-B cable)
FPGA Bank
0
1
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LVDS signals, clocks, PRSNT
Ethernet PHY Status
FPGA Awake LED, Suspend Header
FPGA INIT, DONE
User I/O (active-High)
User I/O (active-High)
User I/O, CPU_RESET (active-High)
6 pins x 2 male header with 8 I/Os
(active-High)
FPGA_PROG_B
Cypress USB to JTAG download cable
logic
Power Management
"Configuration Options."
Table 1-2.
I/O Voltage Rail
2.5V
2.5V
Detailed Description
Schematic
Notes
Page
6
7
8
9
9
9
9
10
9
14, 15
11,12,13
13