Xilinx SP601 User Manual page 24

Chapter 1: SP601 Evaluation Board
Table 1-9: PHY Connections (Cont'd)
X-Ref Target - Figure 1-11
24
FPGA U1
Schematic Netname
Pin
P18 PHY_RXD7
A9 PHY_TXC_GTXCLK
B9 PHY_TXCLK
A8 PHY_TXER
B8 PHY_TXCTL_TXEN
F8 PHY_TXD0
G8 PHY_TXD1
A6 PHY_TXD2
B6 PHY_TXD3
E6 PHY_TXD4
F7 PHY_TXD5
A5 PHY_TXD6
C5 PHY_TXD7
NET "PHY_COL"
NET "PHY_CRS"
NET "PHY_INT"
NET "PHY_MDC"
NET "PHY_MDIO"
NET "PHY_RESET"
NET "PHY_RXCLK"
NET "PHY_RXCTL_RXDV"
NET "PHY_RXD0"
NET "PHY_RXD1"
NET "PHY_RXD2"
NET "PHY_RXD3"
NET "PHY_RXD4"
NET "PHY_RXD5"
NET "PHY_RXD6"
NET "PHY_RXD7"
NET "PHY_RXER"
NET "PHY_TXCLK"
NET "PHY_TXCTL_TXEN"
NET "PHY_TXC_GTXCLK"
NET "PHY_TXD0"
NET "PHY_TXD1"
NET "PHY_TXD2"
NET "PHY_TXD3"
NET "PHY_TXD4"
NET "PHY_TXD5"
NET "PHY_TXD6"
NET "PHY_TXD7"
NET "PHY_TXER"
Figure 1-11: UCF Location Constraints for PHY Connections
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U3 M88E111
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LOC = "L14";
LOC = "M13";
LOC = "J13";
LOC = "N14";
LOC = "P16";
LOC = "L13";
LOC = "L16";
LOC = "N18";
LOC = "M14";
LOC = "U18";
LOC = "U17";
LOC = "T18";
LOC = "T17";
LOC = "N16";
LOC = "N15";
LOC = "P18";
LOC = "P17";
LOC = "B9";
LOC = "B8";
LOC = "A9";
LOC = "F8";
LOC = "G8";
LOC = "A6";
LOC = "B6";
LOC = "E6";
LOC = "F7";
LOC = "A5";
LOC = "C5";
LOC = "A8";
SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009