Xilinx SP601 User Manual page 21

Table 1-7: BPI Memory Connections (Cont'd)
SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
FPGA U1 Pin
H16 FLASH_A6
H15 FLASH_A7
H14 FLASH_A8
H13 FLASH_A9
F18 FLASH_A10
F17 FLASH_A11
K13 FLASH_A12
K12 FLASH_A13
E18 FLASH_A14
E16 FLASH_A15
G13 FLASH_A16
H12 FLASH_A17
D18 FLASH_A18
D17 FLASH_A19
G14 FLASH_A20
F14 FLASH_A21
C18 FLASH_A22
C17 FLASH_A23
F16 FLASH_A24
R13 FPGA_D0_DIN_MISO_MISO1
T14 FPGA_D1_MISO2
V14 FPGA_D2_MISO3
U5 FLASH_D3
V5 FLASH_D4
R3 FLASH_D5
T3 FLASH_D6
R5 FLASH_D7
M16 FLASH_WE_B
L18 FLASH_OE_B
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Schematic Netname
Detailed Description
BPI Memory U10
Pin Number Pin
23 A6
22 A7
20 A8
19 A9
18 A10
17 A11
13 A12
12 A13
11 A14
10 A15
8 A16
7 A17
6 A18
5 A19
4 A20
3 A21
1 A22
30 A23
56 A24
33 DQ0
35 DQ1
38 DQ2
40 DQ3
44 DQ4
46 DQ5
49 DQ6
51 DQ7
55 WE_B
54 OE_B
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