Xilinx SP601 User Manual page 38

Chapter 1: SP601 Evaluation Board
GPIO Male Pin Header
The SP601 provides a 2X6 GPIO male pin header supporting 3.3V power, GND and eight
I/Os.
X-Ref Target - Figure 1-26
GPIO HDR0
GPIO HDR1
GPIO HDR2
GPIO HDR3
Table 1-20: GPIO Header Pins
38
Figure 1-26 and Table 1-20
11
Figure 1-26: GPIO Male Pin Header Topology
FPGA U1 Pin Signal Name
N17 GPIO_HDR0
M18 GPIO_HDR1
A3 GPIO_HDR2
L15 GPIO_HDR3
F15 GPIO_HDR4
B4 GPIO_HDR5
F13 GPIO_HDR6
P12 GPIO_HDR7
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describe the J13 GPIO Male Pin Header.
1 2
3 4
5 6
7 8
9 10
12
J13
VCC3V3
J13 Pin
1
3
5
7
2
4
6
8
GPIO HDR4
GPIO HDR5
GPIO HDR6
GPIO HDR7
UG518_24_070809
SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009