100/1000 Tri-Speed Ethernet Phy - Xilinx SP601 User Manual

5. 10/100/1000 Tri-Speed Ethernet PHY

The SP601 uses the onboard Marvell Alaska PHY device (88E1111) for Ethernet
communications at 10, 100, or 1000 Mb/s. The board supports a GMII/MII interface from
the FPGA to the PHY. The PHY connection to a user-provided Ethernet cable is through a
Halo HFJ11-1G01E RJ-45 connector with built-in magnetics.
On power-up, or on reset, the PHY is configured to operate in GMII mode with PHY
address 0b00111 using the settings shown in
via software commands passed over the MDIO interface.
Table 1-8: PHY Configuration Pins
Table 1-9: PHY Connections
SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
Connection on
Pin
Board Definition and Value
CFG0 V 2.5V
CC
CFG1 Ground
CFG2 V 2.5V
CC
CFG3 V 2.5V
CC
CFG4 V 2.5V HWCFG_MD[2] = 1
CC
CFG5 V 2.5V
CC
CFG6 PHY_LED_RX
FPGA U1
Schematic Netname
Pin
P16 PHY_MDIO
N14 PHY_MDC
J13 PHY_INT
L13 PHY_RESET
M13 PHY_CRS
L14 PHY_COL
L16 PHY_RXCLK
P17 PHY_RXER
N18 PHY_RXCTL_RXDV
M14 PHY_RXD0
U18 PHY_RXD1
U17 PHY_RXD2
T18 PHY_RXD3
T17 PHY_RXD4
N16 PHY_RXD5
N15 PHY_RXD6
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Table 1-8. These settings can be overwritten
Bit[2]
Definition and Value
PHYADR[2] = 1 PHYADR[1] = 1
ENA_PAUSE = 0 PHYADR[4] = 0
ANEG[3] = 1 ANEG[2] = 1
ANEG[0] = 1 ENA_XC = 1
HWCFG_MD[1] = 1
DIS_FC = 1 DIS_SLEEP = 1
SEL_BDT = 0 INT_POL = 1
U3 M88E111
33
35
32
36
115
114
7
8
4
3
128
126
125
124
123
121
Detailed Description
Bit[1] Bit[0]
Definition and Value
PHYADR[0] = 1
PHYADR[3] = 0
ANEG[1] = 1
DIS_125 = 1
HWCFG_MD[0] = 1
HWCFG_MD[3] = 1
75/50 OHM = 0
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