Xilinx SP601 User Manual page 22

Chapter 1: SP601 Evaluation Board
Table 1-7: BPI Memory Connections (Cont'd)
Note:
for larger density devices.
X-Ref Target - Figure 1-10
References
See the Numonyx Flash Memory specifications for more information at
http://www.numonyx.com/Documents/Datasheets/308551_J3D_Discrete_DS.pdf.
In addition, see the Xilinx Spartan-6 Configuration User Guide for more information at
http://www.xilinx.com/support/documentation/user_guides/ug380.pdf.
22
FPGA U1 Pin
L17 FLASH_CE_B
B3 FMC_PWR_GOOD_FLASH_RST_B
Memory U10 pin 56 address A24 is not connected on the 16 MB device. It is made available
NET "FLASH_A0"
NET "FLASH_A1"
NET "FLASH_A2"
NET "FLASH_A3"
NET "FLASH_A4"
NET "FLASH_A5"
NET "FLASH_A6"
NET "FLASH_A7"
NET "FLASH_A8"
NET "FLASH_A9"
NET "FLASH_A10"
NET "FLASH_A11"
NET "FLASH_A12"
NET "FLASH_A13"
NET "FLASH_A14"
NET "FLASH_A15"
NET "FLASH_A16"
NET "FLASH_A17"
NET "FLASH_A18"
NET "FLASH_A19"
NET "FLASH_A20"
NET "FLASH_A21"
NET "FLASH_A22"
NET "FLASH_A23"
NET "FLASH_A24"
NET "FPGA_D0_DIN_MISO_MISO1"
NET "FPGA_D1_MISO2"
NET "FPGA_D2_MISO3"
NET "FLASH_D3"
NET "FLASH_D4"
NET "FLASH_D5"
NET "FLASH_D6"
NET "FLASH_D7"
NET "FLASH_WE_B"
NET "FLASH_OE_B"
NET "FLASH_CE_B"
NET "FMC_PWR_GOOD_FLASH_RST_B"
Figure 1-10: UCF Location Constraints for BPI Flash Connections
www.xilinx.com
Schematic Netname
LOC = "K18";
LOC = "K17";
LOC = "J18";
LOC = "J16";
LOC = "G18";
LOC = "G16";
LOC = "H16";
LOC = "H15";
LOC = "H14";
LOC = "H13";
LOC = "F18";
LOC = "F17";
LOC = "K13";
LOC = "K12";
LOC = "E18";
LOC = "E16";
LOC = "G13";
LOC = "H12";
LOC = "D18";
LOC = "D17";
LOC = "G14";
LOC = "F14";
LOC = "C18";
LOC = "C17";
LOC = "F16";
LOC = "R13";
LOC = "T14";
LOC = "V14";
LOC = "U5";
LOC = "V5";
LOC = "R3";
LOC = "T3";
LOC = "R5";
LOC = "M16";
LOC = "L18";
LOC = "L17";
LOC = "B3";
BPI Memory U10
Pin Number Pin
14 CE0
16 RP_B
SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009