Memory Address Map; Pci To Isa Bus Interrupt Mapping - Intergraph TD-x10 System Reference Manual

58
Address
03E8 - 03EF
03F0 - 03F7
03F8 - 03FF

Memory Address Map

The following table lists the memory address map assignments.
Memory Address
00000000 - 0009FFFF
000A0000 - 000BFFFF
000C0000 - 000C7FFF
000C8000 - 000DFFFF
000E0000 - 000EFFFF
000F0000 - 000FFFFF
00100000 - 0FFFFFFF
10000000 - 3FFFFFFF

PCI to ISA Bus Interrupt Mapping

The ISA bridge (Intel 82379AB) provides the sixteen conventional ISA interrupts, plus four interrupt
request pins for PCI peripheral interrupts (PIRQ0 through PIRQ3). For PC-AT architecture
compatibility reasons, the PCI interrupts are routed to the ISA interrupts within the ISA bridge. The
assertion of a PCI interrupt concludes in an ISA interrupt being asserted.
The 8-bit PIRQ Route Control Registers in the ISA bridge determine to which ISA interrupt a PIRQ is
routed. Four PIRQ Route Control Registers are used for the PCI interrupts, located at the ISA bridge
address offsets defined below.
PCI Interrupt Request
PIRQ0
PIRQ1
PIRQ2
PIRQ3
Bit 7 of each PIRQ registers enable (Low) or disable (High) the routing of the PIRQ to an ISA
interrupt. The lowest four bits (3:0) of each PIRQ register determines to which ISA interrupt the PIRQ
will be routed, as defined below.
Bits (3:0) of PIRQ
0000
0001
0010
0011
0100
0101
Device
Serial Port COM3
I/O Controller
Serial Port COM1
Size
640K
128K
32K
96K
64K
64K
256M
-----
Address Offset (Hex)
60
61
62
63
ISA Interrupt Bits (3:0) of PIRQ
Reserved 1000
Reserved 1001
Reserved 1010
IRQ3 1011
IRQ4 1100
IRQ5 1101
Assignment
System board memory
Video memory
Video ROM
Available I/O Adapter ROM
BIOS ROM and PCMCIA
BIOS ROM
Expansion memory
Reserved
ISA Interrupt
Reserved
IRQ9
IRQ10
IRQ11
IRQ12
Reserved