Memory Address Map; Pci To Isa Bus Interrupt Mapping - Intergraph InterServe 800 System Reference Manual

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Memory Address Map

The following table lists the memory address map assignments.
Memory Address
00000000 - 0009FFFF
000A0000 - 000BFFFF
000C0000 - 000C7FFF
000C8000 - 000DFFFF
000E0000 - 000EFFFF
000F0000 - 000FFFFF
00100000 - 1FFFFFFF
20000000 - 3FFFFFFF

PCI to ISA Bus Interrupt Mapping

The ISA bridge provides the sixteen conventional ISA interrupts, plus four interrupt request
pins for PCI peripheral interrupts (PIRQ0 through PIRQ3). For PC-AT architecture
compatibility reasons, the PCI interrupts are routed to the ISA interrupts within the ISA
bridge. The assertion of a PCI interrupt concludes in an ISA interrupt being asserted.
Bit 7 of each PIRQ registers enable (Low) or disable (High) for the routing of the PIRQ to an
ISA interrupt. The lowest four bits (3:0) of each PIRQ register determines to which ISA
interrupt the PIRQ is routed. You can map the PIRQs to the following ISA interrupts IRQ 5,
10, 11, 15. You can also map to IRQ 3, 4, 7, 12, and 14, but other devices are disabled if
you do so.
Each PCI slot has four available interrupt lines: INTA, INTB, INTC, and INTD. These are
connected to the PCI interrupts, PIRQ0 through PIRQ3, as shown below:
Interrupt
Line
INTA
INTB
INTC
INTD
Size
640K
128K
32K
96K
64K
64K
511M
—
Slot 1 Slot 2 Slot 3
PIRQ0 PIRQ1 PIRQ2
PIRQ1 PIRQ2 PIRQ3
PIRQ2 PIRQ3 PIRQ0
PIRQ3 PIRQ0 PIRQ1
Assignment
System board memory
Video memory
Video ROM
Available I/O Adapter ROM
BIOS ROM and PCMCIA
BIOS ROM
Expansion memory
Reserved
Slot 4 Slot 5
PIRQ3 PIRQ0
PIRQ0 PIRQ1
PIRQ1 PIRQ2
PIRQ2 PIRQ3
Slot 6 Slot 7
PIRQ1 PIRQ2
PIRQ2 PIRQ3
PIRQ3 PIRQ0
PIRQ0 PIRQ1